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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: db05ec0277f5
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  • 3 commits
  • 5 files changed
  • 1 contributor

Commits on Dec 28, 2015

  1. transforms.dead_code_eliminator: update doc.

    whitequark committed Dec 28, 2015
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    57ebd57 View commit details
  2. transforms.cfg_simplifier: implement.

    This allows error reporting in LocalAccessValidator to proceed
    even when the predecessor is an empty block with only a branch.
    whitequark committed Dec 28, 2015
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    8822db0 View commit details
  3. test.coredevice.portability.HostVsDeviceCase.test_misc: update.

    It crashes in a different way now.
    whitequark committed Dec 28, 2015
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    db05ec0 View commit details
2 changes: 2 additions & 0 deletions artiq/compiler/module.py
Original file line number Diff line number Diff line change
@@ -55,6 +55,7 @@ def __init__(self, src, ref_period=1e-6):
artiq_ir_generator = transforms.ARTIQIRGenerator(engine=self.engine,
module_name=src.name,
ref_period=ref_period)
cfg_simplifier = transforms.CFGSimplifier(engine=self.engine)
dead_code_eliminator = transforms.DeadCodeEliminator(engine=self.engine)
local_access_validator = validators.LocalAccessValidator(engine=self.engine)
devirtualization = analyses.Devirtualization()
@@ -70,6 +71,7 @@ def __init__(self, src, ref_period=1e-6):
devirtualization.visit(src.typedtree)
self.artiq_ir = artiq_ir_generator.visit(src.typedtree)
artiq_ir_generator.annotate_calls(devirtualization)
cfg_simplifier.process(self.artiq_ir)
local_access_validator.process(self.artiq_ir)
dead_code_eliminator.process(self.artiq_ir)
interleaver.process(self.artiq_ir)
1 change: 1 addition & 0 deletions artiq/compiler/transforms/__init__.py
Original file line number Diff line number Diff line change
@@ -4,5 +4,6 @@
from .iodelay_estimator import IODelayEstimator
from .artiq_ir_generator import ARTIQIRGenerator
from .dead_code_eliminator import DeadCodeEliminator
from .cfg_simplifier import CFGSimplifier
from .llvm_ir_generator import LLVMIRGenerator
from .interleaver import Interleaver
22 changes: 22 additions & 0 deletions artiq/compiler/transforms/cfg_simplifier.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
"""
:class:`CFGSimplifier` is a simple control flow graph
simplification transform: it removes empty basic blocks.
"""

from .. import ir

class CFGSimplifier:
def __init__(self, engine):
self.engine = engine

def process(self, functions):
for func in functions:
self.process_function(func)

def process_function(self, func):
for block in list(func.basic_blocks):
if len(block.instructions) == 1 and \
isinstance(block.terminator(), ir.Branch):
successor, = block.successors()
block.replace_all_uses_with(successor)
block.erase()
5 changes: 3 additions & 2 deletions artiq/compiler/transforms/dead_code_eliminator.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
"""
:class:`DeadCodeEliminator` is a very simple dead code elimination
transform: it only removes basic blocks with no predecessors.
:class:`DeadCodeEliminator` is a dead code elimination transform:
it only basic blocks with no predecessors as well as unused
instructions without side effects.
"""

from .. import ir
6 changes: 4 additions & 2 deletions artiq/test/coredevice/portability.py
Original file line number Diff line number Diff line change
@@ -42,10 +42,13 @@ def build(self):
self.al = [1, 2, 3, 4, 5]
self.list_copy_in = [2*Hz, 10*MHz]

self.half_input = 0
self.acc = 0
self.list_copy_out = []

@kernel
def run(self):
self.half_input = self.input//2
self.decimal_fraction = Fraction("1.2")
self.acc = 0
for i in range(len(self.al)):
self.acc += self.al[i]
@@ -190,7 +193,6 @@ def test_misc(self):
for f in self.execute, _run_on_host:
uut = f(_Misc)
self.assertEqual(uut.half_input, 42)
self.assertEqual(uut.decimal_fraction, Fraction("1.2"))
self.assertEqual(uut.acc, sum(uut.al))
self.assertEqual(uut.list_copy_in, uut.list_copy_out)