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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: 98ce81bc6d06
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 22, 2015

  1. fhdl/simplify/MemoryToArray: remove spurious memory ports from specials

    @sbourdeauducq
    sbourdeauducq committed Dec 22, 2015
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    2a81389 View commit details

  2. sim: run MemoryToArray before lowering specials

    @sbourdeauducq
    sbourdeauducq committed Dec 22, 2015
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    98ce81b View commit details
Showing with 8 additions and 2 deletions.
  1. +4 −0 migen/fhdl/simplify.py
  2. +4 −2 migen/sim/core.py
4 changes: 4 additions & 0 deletions migen/fhdl/simplify.py
View file
Original file line number Diff line number Diff line change
@@ -55,6 +55,7 @@ def __init__(self):

def transform_fragment(self, i, f):
newspecials = set()
processed_ports = set()

for mem in f.specials:
if not isinstance(mem, Memory):
@@ -111,4 +112,7 @@ def transform_fragment(self, i, f):
sync.append(If(port.we,
storage[port.adr].eq(port.dat_w)))

processed_ports.add(port)

newspecials -= processed_ports
f.specials = newspecials
6 changes: 4 additions & 2 deletions migen/sim/core.py
View file
Original file line number Diff line number Diff line change
@@ -222,6 +222,10 @@ def __init__(self, fragment_or_module, generators, clocks={"sys": 10}, vcd_name=
self.fragment = fragment_or_module
else:
self.fragment = fragment_or_module.get_fragment()

mta = MemoryToArray()
mta.transform_fragment(None, self.fragment)

fs, lowered = lower_specials(overrides={}, specials=self.fragment.specials)
self.fragment += fs
self.fragment.specials -= lowered
@@ -248,8 +252,6 @@ def __init__(self, fragment_or_module, generators, clocks={"sys": 10}, vcd_name=
cd.clk.reset = C(self.time.clocks[clock].high)
self.fragment.clock_domains.append(cd)

mta = MemoryToArray()
mta.transform_fragment(None, self.fragment)
insert_resets(self.fragment)
# comb signals return to their reset value if nothing assigns them
self.fragment.comb[0:0] = [s.eq(s.reset)