Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/artiq
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: f957be4e6f41
Choose a base ref
...
head repository: m-labs/artiq
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 25188f0ca9e2
Choose a head ref
  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 21, 2015

  1. artiq_compile: add missing import.

    whitequark committed Dec 21, 2015
    Copy the full SHA
    ac5c86b View commit details

  2. transforms.interleaver: correctly handle degenerate with parallel: … 

    …blocks.
    whitequark committed Dec 21, 2015
    Copy the full SHA
    25188f0 View commit details
Showing with 13 additions and 4 deletions.
  1. +12 −3 artiq/compiler/transforms/interleaver.py
  2. +1 −1 artiq/frontend/artiq_compile.py
15 changes: 12 additions & 3 deletions artiq/compiler/transforms/interleaver.py
View file
Original file line number Diff line number Diff line change
@@ -73,14 +73,23 @@ def process_function(self, func):
if postdom_tree is None:
postdom_tree = domination.PostDominatorTree(func)

interleave_until = postdom_tree.immediate_dominator(insn.basic_block)
assert (interleave_until is not None) # no nonlocal flow in `with parallel`

target_block = insn.basic_block
target_time = 0
source_blocks = insn.basic_block.successors()
source_times = [0 for _ in source_blocks]

if len(source_blocks) == 1:
# Immediate dominator for a parallel instruction with one successor
# is the first instruction in the body of the statement which created
# it, but below we expect that it would be the first instruction after
# the statement itself.
insn.replace_with(ir.Branch(source_blocks[0]))
continue

interleave_until = postdom_tree.immediate_dominator(insn.basic_block)
assert interleave_until is not None # no nonlocal flow in `with parallel`
assert interleave_until not in source_blocks

while len(source_blocks) > 0:
def time_after_block(pair):
index, block = pair
2 changes: 1 addition & 1 deletion artiq/frontend/artiq_compile.py
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
#!/usr/bin/env python3.5

import sys, logging, argparse
import os, sys, logging, argparse

from artiq.master.databases import DeviceDB, DatasetDB
from artiq.master.worker_db import DeviceManager, DatasetManager