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genlib/fifo: width_or_layout -> width
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sbourdeauducq committed Oct 14, 2015
1 parent 8817716 commit 48d22a7
Showing 1 changed file with 16 additions and 17 deletions.
33 changes: 16 additions & 17 deletions migen/genlib/fifo.py
Original file line number Diff line number Diff line change
@@ -26,38 +26,37 @@ class _FIFOInterface:
Parameters
----------
width_or_layout : int, layout
width : int
Bit width for the data.
depth : int
Depth of the FIFO.
Attributes
----------
din : in, width_or_layout
Input data either flat or Record structured.
din : in, width
Input data
writable : out
There is space in the FIFO and `we` can be asserted to load new data.
we : in
Write enable signal to latch `din` into the FIFO. Does nothing if
`writable` is not asserted.
dout : out, width_or_layout
Output data, same type as `din`. Only valid if `readable` is
asserted.
dout : out, width
Output data. Only valid if `readable` is asserted.
readable : out
Output data `dout` valid, FIFO not empty.
re : in
Acknowledge `dout`. If asserted, the next entry will be
available on the next cycle (if `readable` is high then).
"""
def __init__(self, width_or_layout, depth):
def __init__(self, width, depth):
self.we = Signal()
self.writable = Signal() # not full
self.re = Signal()
self.readable = Signal() # not empty

self.din = Signal(width_or_layout)
self.dout = Signal(width_or_layout)
self.width = width_or_layout
self.din = Signal(width)
self.dout = Signal(width)
self.width = width


class SyncFIFO(Module, _FIFOInterface):
@@ -76,8 +75,8 @@ class SyncFIFO(Module, _FIFOInterface):
"""
__doc__ = __doc__.format(interface=_FIFOInterface.__doc__)

def __init__(self, width_or_layout, depth, fwft=True):
_FIFOInterface.__init__(self, width_or_layout, depth)
def __init__(self, width, depth, fwft=True):
_FIFOInterface.__init__(self, width, depth)

self.level = Signal(max=depth+1)
self.replace = Signal()
@@ -129,9 +128,9 @@ def __init__(self, width_or_layout, depth, fwft=True):


class SyncFIFOBuffered(Module, _FIFOInterface):
def __init__(self, width_or_layout, depth):
_FIFOInterface.__init__(self, width_or_layout, depth)
self.submodules.fifo = fifo = SyncFIFO(width_or_layout, depth, False)
def __init__(self, width, depth):
_FIFOInterface.__init__(self, width, depth)
self.submodules.fifo = fifo = SyncFIFO(width, depth, False)

self.writable = fifo.writable
self.din = fifo.din
@@ -162,8 +161,8 @@ class AsyncFIFO(Module, _FIFOInterface):
"""
__doc__ = __doc__.format(interface=_FIFOInterface.__doc__)

def __init__(self, width_or_layout, depth):
_FIFOInterface.__init__(self, width_or_layout, depth)
def __init__(self, width, depth):
_FIFOInterface.__init__(self, width, depth)

###

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