Revert "sim/core: fix Cat bitshift"

This reverts commit 6d6f91a.
m-labs · Oct 19, 2015 · a824046 · a824046
1 parent 6d6f91a
commit a824046
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/migen/sim/core.py b/migen/sim/core.py
@@ -156,11 +156,10 @@ def assign(self, node, value):
                 value -= 2**node.nbits
             self.modifications[node] = value
         elif isinstance(node, Cat):
-            nbits = 0
             for element in node.l:
-                value >>= nbits
                 nbits = len(element)
                 self.assign(element, value & (2**nbits-1))
+                value >>= nbits
         elif isinstance(node, _Slice):
             full_value = self.eval(node.value, True)
             # clear bits assigned to by the slice