Skip to content

Commit

Permalink
sim/core: fix Cat bitshift
Browse files Browse the repository at this point in the history
sbourdeauducq committed Oct 19, 2015
1 parent 28962ff commit 6d6f91a
Showing 1 changed file with 2 additions and 1 deletion.
3 changes: 2 additions & 1 deletion migen/sim/core.py
Original file line number Diff line number Diff line change
@@ -156,10 +156,11 @@ def assign(self, node, value):
value -= 2**node.nbits
self.modifications[node] = value
elif isinstance(node, Cat):
nbits = 0
for element in node.l:
value >>= nbits
nbits = len(element)
self.assign(element, value & (2**nbits-1))
value >>= nbits
elif isinstance(node, _Slice):
full_value = self.eval(node.value, True)
# clear bits assigned to by the slice

0 comments on commit 6d6f91a

Please sign in to comment.