sim/core: fix Cat bitshift

m-labs · Oct 19, 2015 · 6d6f91a · 6d6f91a
1 parent 28962ff
commit 6d6f91a
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/migen/sim/core.py b/migen/sim/core.py
@@ -156,10 +156,11 @@ def assign(self, node, value):
                 value -= 2**node.nbits
             self.modifications[node] = value
         elif isinstance(node, Cat):
+            nbits = 0
             for element in node.l:
+                value >>= nbits
                 nbits = len(element)
                 self.assign(element, value & (2**nbits-1))
-                value >>= nbits
         elif isinstance(node, _Slice):
             full_value = self.eval(node.value, True)
             # clear bits assigned to by the slice