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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 66b1388a634c
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  • 3 commits
  • 4 files changed
  • 1 contributor

Commits on Nov 23, 2015

  1. Copy the full SHA
    8527e30 View commit details
  2. transforms.interleaver: add a diagnostic for interleave inlining fail…

    …ure.
    whitequark committed Nov 23, 2015
    Copy the full SHA
    fec5c2e View commit details
  3. transforms.artiq_ir_generator: never put TVars in dicts.

    A TVar looks just like whatever it points to, but it does not
    compare equal, nor is its hash the same.
    whitequark committed Nov 23, 2015
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    66b1388 View commit details
9 changes: 5 additions & 4 deletions artiq/compiler/testbench/embedding.py
Original file line number Diff line number Diff line change
@@ -12,15 +12,16 @@ def main():
else:
compile_only = False

ddb_path = os.path.join(os.path.dirname(sys.argv[1]), "device_db.pyon")
dmgr = DeviceManager(DeviceDB(ddb_path))

with open(sys.argv[1]) as f:
testcase_code = compile(f.read(), f.name, "exec")
testcase_vars = {'__name__': 'testbench'}
testcase_vars = {'__name__': 'testbench', 'dmgr': dmgr}
exec(testcase_code, testcase_vars)

ddb_path = os.path.join(os.path.dirname(sys.argv[1]), "device_db.pyon")

try:
core = DeviceManager(DeviceDB(ddb_path)).get("core")
core = dmgr.get("core")
if compile_only:
core.compile(testcase_vars["entrypoint"], (), {})
else:
2 changes: 1 addition & 1 deletion artiq/compiler/transforms/artiq_ir_generator.py
Original file line number Diff line number Diff line change
@@ -1625,7 +1625,7 @@ def visit_CallT(self, node):
method_key = None
if isinstance(node.func, asttyped.AttributeT):
attr_node = node.func
self.method_map[(attr_node.value.type, attr_node.attr)].append(insn)
self.method_map[(attr_node.value.type.find(), attr_node.attr)].append(insn)

if node.iodelay is not None and not iodelay.is_const(node.iodelay, 0):
after_delay = self.add_block()
10 changes: 10 additions & 0 deletions artiq/compiler/transforms/interleaver.py
Original file line number Diff line number Diff line change
@@ -3,6 +3,8 @@
the timestamp would always monotonically nondecrease.
"""

from pythonparser import diagnostic

from .. import types, builtins, ir, iodelay
from ..analyses import domination
from ..algorithms import inline
@@ -127,6 +129,14 @@ def time_after_block(pair):
else: # It's a call.
need_to_inline = len(source_blocks) > 1
if need_to_inline:
if old_decomp.static_target_function is None:
diag = diagnostic.Diagnostic("fatal",
"it is not possible to interleave this function call within "
"a 'with parallel:' statement because the compiler could not "
"prove that the same function would always be called", {},
old_decomp.loc)
self.engine.process(diag)

inline(old_decomp)
postdom_tree = domination.PostDominatorTree(func)
continue
16 changes: 16 additions & 0 deletions lit-test/test/interleaving/error_inlining.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,16 @@
# RUN: %python -m artiq.compiler.testbench.signature +diag %s >%t
# RUN: OutputCheck %s --file-to-check=%t

def f():
delay_mu(2)

def g():
delay_mu(2)

x = f if True else g

def h():
with parallel:
f()
# CHECK-L: ${LINE:+1}: fatal: it is not possible to interleave this function call within a 'with parallel:' statement because the compiler could not prove that the same function would always be called
x()