fhdl/verilog: create clock domains in deterministic order

m-labs · Nov 5, 2015 · 6f5bf02 · 6f5bf02
1 parent 180ba95
commit 6f5bf02
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
@@ -323,7 +323,7 @@ def convert(f, ios=None, name="top",
     if ios is None:
         ios = set()
 
-    for cd_name in list_clock_domains(f):
+    for cd_name in sorted(list_clock_domains(f)):
         try:
             f.clock_domains[cd_name]
         except KeyError: