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fhdl/verilog: create clock domains in deterministic order
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sbourdeauducq committed Nov 5, 2015
1 parent 180ba95 commit 6f5bf02
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion migen/fhdl/verilog.py
Original file line number Diff line number Diff line change
@@ -323,7 +323,7 @@ def convert(f, ios=None, name="top",
if ios is None:
ios = set()

for cd_name in list_clock_domains(f):
for cd_name in sorted(list_clock_domains(f)):
try:
f.clock_domains[cd_name]
except KeyError:

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