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Commits on Oct 29, 2015

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  6. fix typo

    sbourdeauducq committed Oct 30, 2015
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Commits on Oct 31, 2015

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  2. add "blink forever" example

    This is useful for quickly demonstrating the idle kernel.
    sbourdeauducq committed Oct 31, 2015
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Commits on Nov 3, 2015

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  8. Revert "travis/get-xilinx: use http github clone url"

    This reverts commit d06a4d6.
    sbourdeauducq committed Nov 4, 2015
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Commits on Nov 5, 2015

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Commits on Nov 7, 2015

  1. Merge commit 'd0b5c3ba7fb' into new-py2llvm

    whitequark committed Nov 7, 2015
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  2. Merge branch 'master' into new-py2llvm

    whitequark committed Nov 7, 2015
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  3. compiler.types: fix obsolete iodelay references.

    whitequark committed Nov 7, 2015
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  4. Update .gitignore.

    whitequark committed Nov 7, 2015
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Showing with 874 additions and 564 deletions.
  1. +5 −1 .gitignore
  2. +3 −3 .gitmodules
  3. +0 −1 .travis.yml
  4. +2 −0 .travis/get-anaconda.sh
  5. +0 −4 .travis/get-misoc.sh
  6. +2 −0 .travis/get-toolchain.sh
  7. +5 −3 .travis/get-xilinx.sh
  8. +5 −5 artiq/compiler/types.py
  9. +26 −24 artiq/frontend/artiq_flash.sh
  10. +19 −20 artiq/frontend/artiq_gui.py
  11. +6 −1 artiq/frontend/artiq_master.py
  12. +11 −3 artiq/frontend/artiq_run.py
  13. +10 −2 artiq/frontend/thorlabs_tcube_controller.py
  14. +21 −30 artiq/gateware/ad9xxx.py
  15. +7 −9 artiq/gateware/amp/kernel_cpu.py
  16. +2 −2 artiq/gateware/amp/mailbox.py
  17. +1 −1 artiq/gateware/nist_qc1.py
  18. +1 −1 artiq/gateware/nist_qc2.py
  19. +38 −22 artiq/gateware/rtio/core.py
  20. +5 −5 artiq/gateware/rtio/moninj.py
  21. +9 −9 artiq/gateware/rtio/phy/dds.py
  22. +1 −1 artiq/gateware/rtio/phy/ttl_serdes_7series.py
  23. +5 −5 artiq/gateware/rtio/phy/ttl_serdes_generic.py
  24. +1 −1 artiq/gateware/rtio/phy/ttl_serdes_spartan6.py
  25. +1 −1 artiq/gateware/rtio/phy/ttl_simple.py
  26. +5 −5 artiq/gateware/rtio/phy/wishbone.py
  27. +2 −2 artiq/gateware/rtio/rtlink.py
  28. +3 −3 artiq/gateware/soc.py
  29. +63 −21 soc/targets/artiq_kc705.py → artiq/gateware/targets/kc705.py
  30. +36 −12 soc/targets/artiq_pipistrello.py → artiq/gateware/targets/pipistrello.py
  31. +1 −1 artiq/gui/datasets.py
  32. +46 −8 artiq/gui/explorer.py
  33. +148 −58 artiq/gui/log.py
  34. +7 −1 artiq/gui/schedule.py
  35. +8 −0 artiq/master/scheduler.py
  36. +7 −3 artiq/master/worker_impl.py
  37. +68 −0 artiq/runtime/Makefile
  38. 0 {soc → artiq}/runtime/artiq_personality.c
  39. 0 {soc → artiq}/runtime/artiq_personality.h
  40. +0 −4 {soc → artiq}/runtime/bridge.c
  41. 0 {soc → artiq}/runtime/bridge.h
  42. +0 −13 {soc → artiq}/runtime/bridge_ctl.c
  43. +0 −2 {soc → artiq}/runtime/bridge_ctl.h
  44. +1 −1 {soc → artiq}/runtime/clock.c
  45. 0 {soc → artiq}/runtime/clock.h
  46. +0 −13 {soc → artiq}/runtime/dds.c
  47. +0 −1 {soc → artiq}/runtime/dds.h
  48. 0 {soc → artiq}/runtime/flash_storage.c
  49. 0 {soc → artiq}/runtime/flash_storage.h
  50. 0 {soc → artiq}/runtime/isr.c
  51. +37 −3 {soc → artiq}/runtime/kloader.c
  52. +1 −0 {soc → artiq}/runtime/kloader.h
  53. 0 {soc → artiq}/runtime/ksupport.c
  54. 0 {soc → artiq}/runtime/ksupport.h
  55. 0 {soc → artiq}/runtime/ksupport.ld
  56. +66 −0 artiq/runtime/liblwip/Makefile
  57. 0 {soc → artiq}/runtime/liblwip/arch/cc.h
  58. 0 {soc → artiq}/runtime/liblwip/arch/perf.h
  59. 0 {soc → artiq}/runtime/liblwip/arch/sys_arch.h
  60. +1 −1 {soc/runtime/liblwip/netif → artiq/runtime/liblwip}/liteethif.c
  61. 0 {soc/runtime/liblwip/netif → artiq/runtime/liblwip}/liteethif.h
  62. 0 {soc → artiq}/runtime/liblwip/lwipopts.h
  63. 0 {soc → artiq}/runtime/log.c
  64. 0 {soc → artiq}/runtime/log.h
  65. 0 {soc → artiq}/runtime/lwip
  66. 0 {soc → artiq}/runtime/mailbox.c
  67. 0 {soc → artiq}/runtime/mailbox.h
  68. +3 −10 {soc → artiq}/runtime/main.c
  69. +0 −1 {soc → artiq}/runtime/messages.h
  70. 0 {soc → artiq}/runtime/moninj.c
  71. 0 {soc → artiq}/runtime/moninj.h
  72. +2 −2 {soc → artiq}/runtime/net_server.c
  73. 0 {soc → artiq}/runtime/net_server.h
  74. +6 −4 {soc → artiq}/runtime/rtio.c
  75. 0 {soc → artiq}/runtime/rtio.h
  76. +7 −7 {soc → artiq}/runtime/rtiocrg.c
  77. 0 {soc → artiq}/runtime/rtiocrg.h
  78. 0 {soc → artiq}/runtime/runtime.ld
  79. +42 −19 {soc → artiq}/runtime/session.c
  80. +1 −0 {soc → artiq}/runtime/session.h
  81. 0 {soc → artiq}/runtime/test_mode.c
  82. 0 {soc → artiq}/runtime/test_mode.h
  83. 0 {soc → artiq}/runtime/ttl.c
  84. 0 {soc → artiq}/runtime/ttl.h
  85. +3 −1 artiq/tools.py
  86. +7 −18 conda/artiq-kc705-nist_qc1/build.sh
  87. +2 −1 conda/artiq-kc705-nist_qc1/meta.yaml
  88. +7 −18 conda/artiq-kc705-nist_qc2/build.sh
  89. +2 −1 conda/artiq-kc705-nist_qc2/meta.yaml
  90. +6 −17 conda/artiq-pipistrello-nist_qc1/build.sh
  91. +2 −1 conda/artiq-pipistrello-nist_qc1/meta.yaml
  92. +0 −1 conda/artiq/meta.yaml
  93. +40 −18 doc/manual/installing.rst
  94. +12 −2 doc/manual/management_system.rst
  95. +2 −2 doc/manual/utilities.rst
  96. +3 −0 examples/master/device_db.pyon
  97. +13 −0 examples/master/repository/blink_forever.py
  98. +11 −3 examples/master/repository/dds_setter.py
  99. +17 −0 examples/master/repository/terminate_all.py
  100. +0 −77 soc/runtime/Makefile
  101. +0 −55 soc/runtime/liblwip/Makefile
6 changes: 5 additions & 1 deletion .gitignore
Original file line number Diff line number Diff line change
@@ -6,7 +6,6 @@ __pycache__
*.elf
*.fbi
*.pyc
soc/runtime/service_table.h
doc/manual/_build
/build
/dist
@@ -19,3 +18,8 @@ examples/master/dataset_db.pyon
examples/sim/dataset_db.pyon
Output/
/lit-test/libartiq_support/libartiq_support.so

# for developer convenience
/test*.py
/device_db.pyon
/dataset_db.pyon
6 changes: 3 additions & 3 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
[submodule "soc/runtime/lwip"]
path = soc/runtime/lwip
[submodule "artiq/runtime/lwip"]
path = artiq/runtime/lwip
url = git://git.savannah.nongnu.org/lwip.git
ignore = untracked
ignore = untracked
1 change: 0 additions & 1 deletion .travis.yml
Original file line number Diff line number Diff line change
@@ -18,7 +18,6 @@ install:
- if [ $TRAVIS_PULL_REQUEST != false ]; then BUILD_SOC=none; fi
- if [ $BUILD_SOC != none ]; then ./.travis/get-xilinx.sh; fi
- if [ $BUILD_SOC != none ]; then ./.travis/get-toolchain.sh; fi
- if [ $BUILD_SOC != none ]; then ./.travis/get-misoc.sh; fi
- . ./.travis/get-anaconda.sh
- source $HOME/miniconda/bin/activate py35
- conda install -q pip coverage anaconda-client cython
2 changes: 2 additions & 0 deletions .travis/get-anaconda.sh
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
#!/bin/sh
# Copyright (C) 2014, 2015 Robert Jordens <jordens@gmail.com>

set -e

export PATH=$HOME/miniconda/bin:$PATH
wget http://repo.continuum.io/miniconda/Miniconda3-latest-Linux-x86_64.sh -O miniconda.sh
bash miniconda.sh -b -p $HOME/miniconda
4 changes: 0 additions & 4 deletions .travis/get-misoc.sh

This file was deleted.

2 changes: 2 additions & 0 deletions .travis/get-toolchain.sh
Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
#!/bin/sh

set -e

packages="http://us.archive.ubuntu.com/ubuntu/pool/universe/i/iverilog/iverilog_0.9.7-1_amd64.deb"

mkdir -p packages
8 changes: 5 additions & 3 deletions .travis/get-xilinx.sh
Original file line number Diff line number Diff line change
@@ -2,6 +2,8 @@
# Copyright (C) 2014, 2015 M-Labs Limited
# Copyright (C) 2014, 2015 Robert Jordens <jordens@gmail.com>

set -e

wget http://sionneau.net/artiq/Xilinx/xilinx_ise_14.7_s3_s6.tar.gz.gpg
echo "$secret" | gpg --passphrase-fd 0 xilinx_ise_14.7_s3_s6.tar.gz.gpg
tar -C $HOME/ -xzf xilinx_ise_14.7_s3_s6.tar.gz
@@ -26,13 +28,13 @@ echo "$secret" | gpg --passphrase-fd 0 Xilinx.lic.gpg
mkdir -p ~/.Xilinx
mv Xilinx.lic ~/.Xilinx/Xilinx.lic

git clone https://github.com/fallen/impersonate_macaddress
git clone https://github.com/m-labs/impersonate_macaddress
make -C impersonate_macaddress
# Tell mibuild where Xilinx toolchains are installed
# and feed it the mac address corresponding to the license
cat >> $HOME/.m-labs/build_settings.sh << EOF
MISOC_EXTRA_VIVADO_CMDLINE="-Ob vivado_path $HOME/Xilinx/Vivado"
MISOC_EXTRA_ISE_CMDLINE="-Ob ise_path $HOME/opt/Xilinx/"
MISOC_EXTRA_ISE_CMDLINE="--gateware-toolchain-path $HOME/opt/Xilinx/"
MISOC_EXTRA_VIVADO_CMDLINE="--gateware-toolchain-path $HOME/Xilinx/Vivado"
export MACADDR=$macaddress
export LD_PRELOAD=$PWD/impersonate_macaddress/impersonate_macaddress.so
EOF
10 changes: 5 additions & 5 deletions artiq/compiler/types.py
Original file line number Diff line number Diff line change
@@ -262,9 +262,9 @@ class TRPCFunction(TFunction):
attributes = OrderedDict()

def __init__(self, args, optargs, ret, service):
super().__init__(args, optargs, ret,
delay=FixedDelay(iodelay.Constant(0)))
super().__init__(args, optargs, ret)
self.service = service
self.delay = TFixedDelay(iodelay.Const(0))

def unify(self, other):
if isinstance(other, TRPCFunction) and \
@@ -285,9 +285,9 @@ class TCFunction(TFunction):
attributes = OrderedDict()

def __init__(self, args, ret, name):
super().__init__(args, OrderedDict(), ret,
delay=FixedDelay(iodelay.Constant(0)))
self.name = name
super().__init__(args, OrderedDict(), ret)
self.name = name
self.delay = TFixedDelay(iodelay.Const(0))

def unify(self, other):
if isinstance(other, TCFunction) and \
50 changes: 26 additions & 24 deletions artiq/frontend/artiq_flash.sh
Original file line number Diff line number Diff line change
@@ -11,17 +11,14 @@ def run(script):
file.close()

run("""
# exit on error
set -e
# print commands
#set -x
ARTIQ_PREFIX=$(python3 -c "import artiq; print(artiq.__path__[0])")
# Default is kc705
BOARD=kc705
# Default mezzanine board is nist_qc1
MEZZANINE_BOARD=nist_qc1
# Default hardware adapter is qc1
HARDWARE_ADAPTER=qc1
while getopts "bBrht:d:f:m:" opt
do
@@ -67,14 +64,14 @@ do
fi
;;
m)
if [ "$OPTARG" == "nist_qc1" ]
if [ "$OPTARG" == "qc1" ]
then
MEZZANINE_BOARD=nist_qc1
elif [ "$OPTARG" == "nist_qc2" ]
HARDWARE_ADAPTER=qc1
elif [ "$OPTARG" == "qc2" ]
then
MEZZANINE_BOARD=nist_qc2
HARDWARE_ADAPTER=qc2
else
echo "KC705 mezzanine board is either nist_qc1 or nist_qc2"
echo "Hardware adapter should be qc1 or qc2"
exit 1
fi
;;
@@ -88,8 +85,8 @@ do
echo "-B Flash BIOS"
echo "-r Flash ARTIQ runtime"
echo "-h Show this help message"
echo "-t Target (kc705, pipistrello, default is: kc705)"
echo "-m Mezzanine board (nist_qc1, nist_qc2, default is: nist_qc1)"
echo "-t Target (kc705/pipistrello, default: kc705)"
echo "-m Hardware adapter (qc1/qc2, default: qc1)"
echo "-f Flash storage image generated with artiq_mkfs"
echo "-d Directory containing the binaries to be flashed"
exit 1
@@ -129,30 +126,28 @@ fi
if [ "$BOARD" == "kc705" ]
then
UDEV_RULES=99-kc705.rules
BITSTREAM=artiq_kc705-${MEZZANINE_BOARD}-kc705.bit
CABLE=jtaghs1_fast
PROXY=bscan_spi_kc705.bit
BIOS_ADDR=0xaf0000
RUNTIME_ADDR=0xb00000
RUNTIME_FILE=runtime.fbi
FS_ADDR=0xb40000
if [ -z "$BIN_PREFIX" ]
then
RUNTIME_FILE=${MEZZANINE_BOARD}/runtime.fbi
BIN_PREFIX=$ARTIQ_PREFIX/binaries/kc705
BIN_PREFIX=$ARTIQ_PREFIX/binaries/kc705-$HARDWARE_ADAPTER
fi
search_for_proxy $PROXY
elif [ "$BOARD" == "pipistrello" ]
then
UDEV_RULES=99-papilio.rules
BITSTREAM=artiq_pipistrello-nist_qc1-pipistrello.bit
CABLE=papilio
PROXY=bscan_spi_lx45_csg324.bit
BIOS_ADDR=0x170000
RUNTIME_ADDR=0x180000
RUNTIME_FILE=runtime.fbi
FS_ADDR=0x1c0000
if [ -z "$BIN_PREFIX" ]; then BIN_PREFIX=$ARTIQ_PREFIX/binaries/pipistrello; fi
if [ -z "$BIN_PREFIX" ];
then
BIN_PREFIX=$ARTIQ_PREFIX/binaries/pipistrello-$HARDWARE_ADAPTER
fi
search_for_proxy $PROXY
fi
@@ -166,9 +161,17 @@ fi
set +e
xc3sprog -c $CABLE -R > /dev/null 2>&1
if [ "$?" != "0" ]
STATUS=$?
set -e
if [ "$STATUS" == "127" ]
then
echo "Flashing failed. Maybe you do not have permission to access the USB device?"
echo "xc3sprog not found. Please install it or check your PATH."
exit
fi
if [ "$STATUS" != "0" ]
then
echo "Failed to connect to FPGA."
echo "Maybe you do not have permission to access the USB device?"
echo "To fix this you might want to add a udev rule by doing:"
echo "$ sudo cp $ARTIQ_PREFIX/misc/$UDEV_RULES /etc/udev/rules.d"
echo "Then unplug/replug your device and try flashing again"
@@ -177,7 +180,6 @@ then
echo "Please make sure you used the correct -t option (currently: $BOARD)"
exit
fi
set -e
if [ ! -z "$FILENAME" ]
then
@@ -188,7 +190,7 @@ fi
if [ "${FLASH_BITSTREAM}" == "1" ]
then
echo "Flashing FPGA bitstream..."
xc3sprog -v -c $CABLE -I$PROXY_PATH/$PROXY $BIN_PREFIX/$BITSTREAM:w:0x0:BIT
xc3sprog -v -c $CABLE -I$PROXY_PATH/$PROXY $BIN_PREFIX/top.bit:w:0x0:BIT
fi
if [ "${FLASH_BIOS}" == "1" ]
@@ -200,7 +202,7 @@ fi
if [ "${FLASH_RUNTIME}" == "1" ]
then
echo "Flashing ARTIQ runtime..."
xc3sprog -v -c $CABLE -I$PROXY_PATH/$PROXY $BIN_PREFIX/${RUNTIME_FILE}:w:$RUNTIME_ADDR:BIN
xc3sprog -v -c $CABLE -I$PROXY_PATH/$PROXY $BIN_PREFIX/runtime.fbi:w:$RUNTIME_ADDR:BIN
fi
echo "Done."
xc3sprog -v -c $CABLE -R > /dev/null 2>&1
39 changes: 19 additions & 20 deletions artiq/frontend/artiq_gui.py
Original file line number Diff line number Diff line change
@@ -10,7 +10,7 @@
from quamash import QEventLoop, QtGui, QtCore
from pyqtgraph import dockarea

from artiq.tools import verbosity_args, init_logger
from artiq.tools import verbosity_args, init_logger, artiq_dir
from artiq.protocols.pc_rpc import AsyncioClient
from artiq.gui.state import StateManager
from artiq.gui.explorer import ExplorerDock
@@ -21,10 +21,6 @@
from artiq.gui.console import ConsoleDock


data_dir = os.path.join(os.path.abspath(os.path.dirname(__file__)),
"..", "gui")


def get_argparser():
parser = argparse.ArgumentParser(description="ARTIQ GUI client")
parser.add_argument(
@@ -46,7 +42,8 @@ def get_argparser():
class MainWindow(QtGui.QMainWindow):
def __init__(self, app, server):
QtGui.QMainWindow.__init__(self)
self.setWindowIcon(QtGui.QIcon(os.path.join(data_dir, "icon.png")))
icon = QtGui.QIcon(os.path.join(artiq_dir, "gui", "icon.png"))
self.setWindowIcon(icon)
self.setWindowTitle("ARTIQ - {}".format(server))
self.exit_request = asyncio.Event()

@@ -67,14 +64,17 @@ def main():
app = QtGui.QApplication([])
loop = QEventLoop(app)
asyncio.set_event_loop(loop)
atexit.register(lambda: loop.close())
atexit.register(loop.close)

smgr = StateManager(args.db_file)
rpc_clients = dict()
for target in "schedule", "repository", "dataset_db":
client = AsyncioClient()
loop.run_until_complete(client.connect_rpc(
args.server, args.port_control, "master_" + target))
atexit.register(client.close_rpc)
rpc_clients[target] = client

schedule_ctl = AsyncioClient()
loop.run_until_complete(schedule_ctl.connect_rpc(
args.server, args.port_control, "master_schedule"))
atexit.register(lambda: schedule_ctl.close_rpc())
smgr = StateManager(args.db_file)

win = MainWindow(app, args.server)
area = dockarea.DockArea()
@@ -85,7 +85,9 @@ def main():
status_bar.showMessage("Connected to {}".format(args.server))
win.setStatusBar(status_bar)

d_explorer = ExplorerDock(win, status_bar, schedule_ctl)
d_explorer = ExplorerDock(win, status_bar,
rpc_clients["schedule"],
rpc_clients["repository"])
smgr.register(d_explorer)
loop.run_until_complete(d_explorer.sub_connect(
args.server, args.port_notify))
@@ -110,25 +112,22 @@ def main():
area.addDock(d_datasets, "top")
area.addDock(d_explorer, "above", d_datasets)

d_schedule = ScheduleDock(status_bar, schedule_ctl)
d_schedule = ScheduleDock(status_bar, rpc_clients["schedule"])
loop.run_until_complete(d_schedule.sub_connect(
args.server, args.port_notify))
atexit.register(lambda: loop.run_until_complete(d_schedule.sub_close()))
d_explorer.get_current_schedule = d_schedule.get_current_schedule

d_log = LogDock()
smgr.register(d_log)
loop.run_until_complete(d_log.sub_connect(
args.server, args.port_notify))
atexit.register(lambda: loop.run_until_complete(d_log.sub_close()))

dataset_db = AsyncioClient()
loop.run_until_complete(dataset_db.connect_rpc(
args.server, args.port_control, "master_dataset_db"))
atexit.register(lambda: dataset_db.close_rpc())
def _set_dataset(k, v):
asyncio.ensure_future(dataset_db.set(k, v))
asyncio.ensure_future(rpc_clients["dataset_db"].set(k, v))
def _del_dataset(k):
asyncio.ensure_future(dataset_db.delete(k))
asyncio.ensure_future(rpc_clients["dataset_db"].delete(k))
d_console = ConsoleDock(
d_datasets.get_dataset,
_set_dataset,
7 changes: 6 additions & 1 deletion artiq/frontend/artiq_master.py
Original file line number Diff line number Diff line change
@@ -83,7 +83,12 @@ def main():
"log": log_worker
}
scheduler = Scheduler(get_last_rid() + 1, worker_handlers, repo_backend)
worker_handlers["scheduler_submit"] = scheduler.submit
worker_handlers.update({
"scheduler_submit": scheduler.submit,
"scheduler_delete": scheduler.delete,
"scheduler_request_termination": scheduler.request_termination,
"scheduler_get_status": scheduler.get_status
})
scheduler.start()
atexit.register(lambda: loop.run_until_complete(scheduler.stop()))

14 changes: 11 additions & 3 deletions artiq/frontend/artiq_run.py
Original file line number Diff line number Diff line change
@@ -38,20 +38,28 @@ def run(self):

class DummyScheduler:
def __init__(self):
self.next_rid = 0
self.rid = 0
self.pipeline_name = "main"
self.priority = 0
self.expid = None

self._next_rid = 1

def submit(self, pipeline_name, expid, priority, due_date, flush):
rid = self.next_rid
self.next_rid += 1
rid = self._next_rid
self._next_rid += 1
logger.info("Submitting: %s, RID=%s", expid, rid)
return rid

def delete(self, rid):
logger.info("Deleting RID %s", rid)

def request_termination(self, rid):
logger.info("Requesting termination of RID %s", rid)

def get_status(self):
return dict()

def pause(self):
pass

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