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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 45a36c2a7c47
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  • 3 commits
  • 2 files changed
  • 2 contributors

Commits on Nov 8, 2015

  1. Fix CSRBankArray

    @fallen @sbourdeauducq
    fallen authored and sbourdeauducq committed Nov 8, 2015
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    2963296 View commit details

  2. replace Counter in Converters

    @fallen @sbourdeauducq
    fallen authored and sbourdeauducq committed Nov 8, 2015
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    127edc0 View commit details

  3. wishbone: update TODO

    @sbourdeauducq
    sbourdeauducq committed Nov 8, 2015
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    45a36c2 View commit details
Showing with 32 additions and 18 deletions.
  1. +1 −1 misoc/interconnect/csr_bus.py
  2. +31 −17 misoc/interconnect/wishbone.py
2 changes: 1 addition & 1 deletion misoc/interconnect/csr_bus.py
View file
Original file line number Diff line number Diff line change
@@ -156,7 +156,7 @@ def scan(self, ifargs, ifkwargs):
if mapaddr is None:
continue
sram_bus = Interface(*ifargs, **ifkwargs)
mmap = csr.SRAM(memory, mapaddr, bus=sram_bus)
mmap = SRAM(memory, mapaddr, bus=sram_bus)
self.submodules += mmap
csrs += mmap.get_csrs()
self.srams.append((name, memory, mapaddr, mmap))
48 changes: 31 additions & 17 deletions misoc/interconnect/wishbone.py
View file
Original file line number Diff line number Diff line change
@@ -9,7 +9,7 @@

from misoc.interconnect import csr

# TODO: rewrite without FlipFlop and Counter
# TODO: rewrite without FlipFlop


_layout = [
@@ -177,15 +177,22 @@ def __init__(self, master, slave):
read = Signal()
write = Signal()

counter = Counter(max=ratio)
self.submodules += counter
counter = Signal(max=ratio)
counter_reset = Signal()
counter_ce = Signal()
self.sync += \
If(counter_reset,
counter.eq(0)
).Elif(counter_ce,
counter.eq(counter + 1)
)
counter_done = Signal()
self.comb += counter_done.eq(counter.value == ratio-1)
self.comb += counter_done.eq(counter == ratio-1)

# Main FSM
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
counter.reset.eq(1),
counter_reset.eq(1),
If(master.stb & master.cyc,
If(master.we,
NextState("WRITE")
@@ -201,7 +208,7 @@ def __init__(self, master, slave):
If(master.stb & master.cyc,
slave.stb.eq(1),
If(slave.ack,
counter.ce.eq(1),
counter_ce.eq(1),
If(counter_done,
master.ack.eq(1),
NextState("IDLE")
@@ -217,7 +224,7 @@ def __init__(self, master, slave):
If(master.stb & master.cyc,
slave.stb.eq(1),
If(slave.ack,
counter.ce.eq(1),
counter_ce.eq(1),
If(counter_done,
master.ack.eq(1),
NextState("IDLE")
@@ -235,7 +242,7 @@ def __init__(self, master, slave):
).Else(
slave.cti.eq(2)
),
slave.adr.eq(Cat(counter.value, master.adr))
slave.adr.eq(Cat(counter, master.adr))
]

# Datapath
@@ -245,13 +252,13 @@ def __init__(self, master, slave):
slave.sel.eq(master.sel[i*dw_to//8:(i+1)*dw_to]),
slave.dat_w.eq(master.dat_w[i*dw_to:(i+1)*dw_to])
]
self.comb += Case(counter.value, cases)
self.comb += Case(counter, cases)


cached_data = Signal(dw_from)
self.comb += master.dat_r.eq(Cat(cached_data[dw_to:], slave.dat_r))
self.sync += \
If(read & counter.ce,
If(read & counter_ce,
cached_data.eq(master.dat_r)
)

@@ -291,13 +298,20 @@ def __init__(self, master, slave):
self.submodules += address
self.comb += address.d.eq(master.adr)

counter = Counter(max=ratio)
self.submodules += counter
counter = Signal(max=ratio)
counter_ce = Signal()
counter_reset = Signal()
self.sync += \
If(counter_reset,
counter.eq(0)
).Elif(counter_ce,
counter.eq(counter + 1)
)
counter_offset = Signal(max=ratio)
counter_done = Signal()
self.comb += [
counter_offset.eq(address.q),
counter_done.eq((counter.value + counter_offset) == ratio-1)
counter_done.eq((counter + counter_offset) == ratio-1)
]

cached_data = Signal(dw_to)
@@ -318,7 +332,7 @@ def __init__(self, master, slave):
# Main FSM
self.submodules.fsm = fsm = FSM()
fsm.act("IDLE",
counter.reset.eq(1),
counter_reset.eq(1),
If(master.stb & master.cyc,
address.ce.eq(1),
If(master.we,
@@ -335,7 +349,7 @@ def __init__(self, master, slave):
fsm.act("WRITE",
If(master.stb & master.cyc,
write.eq(1),
counter.ce.eq(1),
counter_ce.eq(1),
master.ack.eq(1),
If(counter_done,
NextState("EVICT")
@@ -388,7 +402,7 @@ def __init__(self, master, slave):
write_sel = Signal()
cases[i] = write_sel.eq(1)
self.comb += [
cached_sels[i].reset.eq(counter.reset),
cached_sels[i].reset.eq(counter_reset),
If(write,
cached_datas[i].d.eq(master.dat_w),
).Else(
@@ -400,7 +414,7 @@ def __init__(self, master, slave):
cached_sels[i].ce.eq(1)
)
]
self.comb += Case(counter.value + counter_offset, cases)
self.comb += Case(counter + counter_offset, cases)

cases = {}
for i in range(ratio):