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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 6869f0998027
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  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Nov 16, 2015

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    bccac84 View commit details

Commits on Nov 17, 2015

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    029bd6c View commit details
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    6869f09 View commit details
Showing with 28 additions and 0 deletions.
  1. +2 −0 misoc/integration/soc_core.py
  2. +9 −0 misoc/interconnect/csr.py
  3. +17 −0 misoc/interconnect/csr_bus.py
2 changes: 2 additions & 0 deletions misoc/integration/soc_core.py
Original file line number Diff line number Diff line change
@@ -183,6 +183,8 @@ def do_finalize(self):
self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory)
for name, constant in self.csrbankarray.constants:
self.add_constant((name + "_" + constant.name).upper(), constant.value)

# Interrupts
for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
9 changes: 9 additions & 0 deletions misoc/interconnect/csr.py
Original file line number Diff line number Diff line change
@@ -12,6 +12,14 @@ def __init__(self, size, name):
self.size = size


class CSRConstant(Constant):
def __init__(self, value, bits_sign=None, name=None):
Constant.__init__(self, value, bits_sign)
self.name = get_obj_var_name(name)
if self.name is None:
raise ValueError("Cannot extract CSR name from code, need to specify.")


class CSR(_CSRBase):
def __init__(self, size=1, name=None):
_CSRBase.__init__(self, size, name)
@@ -131,6 +139,7 @@ def gatherer(self):
class AutoCSR:
get_memories = _make_gatherer("get_memories", Memory, memprefix)
get_csrs = _make_gatherer("get_csrs", _CSRBase, csrprefix)
get_constants = _make_gatherer("get_constants", CSRConstant, csrprefix)


class GenericBank(Module):
17 changes: 17 additions & 0 deletions misoc/interconnect/csr_bus.py
Original file line number Diff line number Diff line change
@@ -20,6 +20,19 @@ def __init__(self, data_width=8, address_width=14):
Record.__init__(self, set_layout_parameters(_layout,
data_width=data_width, address_width=address_width))

def write(self, adr, dat):
yield self.adr.eq(adr)
yield self.dat_w.eq(dat)
yield self.we.eq(1)
yield
yield self.we.eq(0)

def read(self, adr):
yield self.adr.eq(adr)
yield
yield
return (yield self.dat_r)


class Interconnect(Module):
def __init__(self, master, slaves):
@@ -144,6 +157,7 @@ def __init__(self, source, address_map, *ifargs, **ifkwargs):
def scan(self, ifargs, ifkwargs):
self.banks = []
self.srams = []
self.constants = []
for name, obj in xdir(self.source, True):
if hasattr(obj, "get_csrs"):
csrs = obj.get_csrs()
@@ -165,6 +179,9 @@ def scan(self, ifargs, ifkwargs):
self.submodules += mmap
csrs += mmap.get_csrs()
self.srams.append((name, memory, mapaddr, mmap))
if hasattr(obj, "get_constants"):
for constant in obj.get_constants():
self.constants.append((name, constant))
if csrs:
mapaddr = self.address_map(name, None)
if mapaddr is None: