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Commits on Sep 22, 2015

  1. misoclib -> misoc

    sbourdeauducq committed Sep 22, 2015
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  2. migen.fhdl.std -> migen

    sbourdeauducq committed Sep 22, 2015
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  3. CONTRIBUTING.md->rst

    sbourdeauducq committed Sep 22, 2015
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Commits on Sep 23, 2015

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  2. setup: cleanup

    sbourdeauducq committed Sep 23, 2015
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Commits on Sep 24, 2015

  1. cores directory

    sbourdeauducq committed Sep 24, 2015
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Commits on Sep 25, 2015

  1. fix most imports

    sbourdeauducq committed Sep 25, 2015
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Commits on Sep 26, 2015

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  2. replace flen with len

    sbourdeauducq committed Sep 26, 2015
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  3. sdram working on PPro

    sbourdeauducq committed Sep 26, 2015
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  4. Revert "Use shutil rather then rm -rf command."

    This reverts commit d8fd4fe.
    sbourdeauducq committed Sep 26, 2015
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  5. Revert "Use shutil rather then rm -rf command."

    This reverts commit d8fd4fe.
    sbourdeauducq committed Sep 26, 2015
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Commits on Sep 27, 2015

  1. Sort constants in csr generation.

    Previously the order of constant output depended on Python's hashing order
    which changes every run. This caused the file to change every run.
    
    With this change the csr.h file will always be the same. This can be verified
    this with the following;
    ```bash
     CSR=software/include/generated/csr.h
     for i in 1 2 3 4 5 6; do
       rm -f $CSR; python make.py build-headers
       cp $CSR $CSR.$i
     done
     md5sum $CSR.*
    ```
    mithro authored and sbourdeauducq committed Sep 27, 2015
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  2. Sort constants in csr generation.

    Previously the order of constant output depended on Python's hashing order
    which changes every run. This caused the file to change every run.
    
    With this change the csr.h file will always be the same. This can be verified
    this with the following;
    ```bash
     CSR=software/include/generated/csr.h
     for i in 1 2 3 4 5 6; do
       rm -f $CSR; python make.py build-headers
       cp $CSR $CSR.$i
     done
     md5sum $CSR.*
    ```
    mithro authored and sbourdeauducq committed Sep 27, 2015
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Commits on Sep 28, 2015

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  2. Fix typo.

    whitequark committed Sep 28, 2015
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  4. Revert "Sort constants in csr generation."

    This reverts commit d628c14.
    sbourdeauducq committed Sep 28, 2015
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Commits on Sep 29, 2015

  1. minor fixes

    sbourdeauducq committed Sep 29, 2015
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  3. cores/gpio: fix import

    sbourdeauducq committed Sep 29, 2015
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  4. flterm: cleanup

    sbourdeauducq committed Sep 29, 2015
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Commits on Sep 30, 2015

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Commits on Oct 2, 2015

  1. sdram: cleanup

    sbourdeauducq committed Oct 2, 2015
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Commits on Oct 4, 2015

  1. setup: fix readme

    sbourdeauducq committed Oct 4, 2015
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Commits on Oct 5, 2015

  1. setup: include software and Verilog files

    Broken on Python 3.5
    error: can't copy 'misoc/software': doesn't exist or not a regular file
    sbourdeauducq committed Oct 5, 2015
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Commits on Oct 13, 2015

  1. software/bios: move romboot after serialboot and netboot

    On designs using romboot (firmware embedded in ram blocks), we generally upload new firmwares with serialboot and netboot for prototyping.
    Moving romboot after serialboot and netboot avoid manual interrupts of the boot sequence.
    enjoy-digital committed Oct 13, 2015
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  2. software/bios: move romboot after serialboot and netboot

    On designs using romboot (firmware embedded in ram blocks), we generally upload new firmwares with serialboot and netboot for prototyping.
    Moving romboot after serialboot and netboot avoid manual interrupts of the boot sequence.
    enjoy-digital committed Oct 13, 2015
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Commits on Oct 14, 2015

  1. integration/builder: fix building for SoCSDRAM-based targets when SDR…

    …AM is disabled
    
    Reported by Florent Kermarrec
    sbourdeauducq committed Oct 14, 2015
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Commits on Oct 19, 2015

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Commits on Oct 23, 2015

  1. cores: fix liteeth

    enjoy-digital committed Oct 23, 2015
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Commits on Oct 24, 2015

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Commits on Nov 1, 2015

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Showing with 3,537 additions and 3,283 deletions.
  1. +2 −12 .gitignore
  2. +10 −10 .gitmodules
  3. +36 −0 .travis.yml
  4. 0 CONTRIBUTING.md → CONTRIBUTING.rst
  5. +4 −0 MANIFEST.in
  6. +1 −1 README
  7. 0 build/.keep_me
  8. +1 −0 conda/misoc/bld.bat
  9. +26 −0 conda/misoc/meta.yaml
  10. +0 −20 crc.py
  11. 0 extcores/__init__.py
  12. +0 −1 extcores/mor1kx/submodule
  13. +0 −32 flash_extra.py
  14. +0 −222 make.py
  15. 0 {targets → misoc}/__init__.py
  16. 0 {misoclib/video → misoc/cores}/__init__.py
  17. +7 −7 {misoclib/mem/sdram/phy → misoc/cores}/dfii.py
  18. +1 −0 misoc/cores/dvi_sampler/__init__.py
  19. +3 −4 {misoclib/video/dvisampler → misoc/cores/dvi_sampler}/analysis.py
  20. +8 −6 {misoclib/video/dvisampler → misoc/cores/dvi_sampler}/chansync.py
  21. +7 −5 {misoclib/video/dvisampler → misoc/cores/dvi_sampler}/charsync.py
  22. +3 −2 {misoclib/video/dvisampler → misoc/cores/dvi_sampler}/clocking.py
  23. 0 {misoclib/video/dvisampler → misoc/cores/dvi_sampler}/common.py
  24. +11 −11 misoclib/video/dvisampler/__init__.py → misoc/cores/dvi_sampler/core.py
  25. +3 −2 {misoclib/video/dvisampler → misoc/cores/dvi_sampler}/datacapture.py
  26. +7 −6 {misoclib/video/dvisampler → misoc/cores/dvi_sampler}/debug.py
  27. +2 −2 {misoclib/video/dvisampler → misoc/cores/dvi_sampler}/decoding.py
  28. +7 −5 {misoclib/video/dvisampler → misoc/cores/dvi_sampler}/dma.py
  29. +4 −2 {misoclib/video/dvisampler → misoc/cores/dvi_sampler}/edid.py
  30. +8 −6 {misoclib/video/dvisampler → misoc/cores/dvi_sampler}/wer.py
  31. +1 −0 misoc/cores/framebuffer/__init__.py
  32. +4 −4 misoclib/video/framebuffer/__init__.py → misoc/cores/framebuffer/core.py
  33. +8 −5 {misoclib/video → misoc/cores}/framebuffer/dvi.py
  34. +1 −1 {misoclib/video → misoc/cores}/framebuffer/format.py
  35. +3 −3 {misoclib/video → misoc/cores}/framebuffer/phy.py
  36. +5 −4 {misoclib/com → misoc/cores}/gpio.py
  37. +14 −0 misoc/cores/identifier.py
  38. +1 −0 misoc/cores/lasmicon/__init__.py
  39. +12 −7 {misoclib/mem/sdram/core → misoc/cores}/lasmicon/bankmachine.py
  40. +18 −28 misoclib/mem/sdram/core/lasmicon/__init__.py → misoc/cores/lasmicon/core.py
  41. +13 −19 {misoclib/mem/sdram/core → misoc/cores}/lasmicon/multiplexer.py
  42. +3 −2 {misoclib/mem/sdram/core → misoc/cores}/lasmicon/perf.py
  43. +69 −0 misoc/cores/lasmicon/refresher.py
  44. +4 −4 misoclib/mem/sdram/test/bankmachine_tb.py → misoc/cores/lasmicon/test_bankmachine.py
  45. +2 −2 misoclib/mem/sdram/test/common.py → misoc/cores/lasmicon/test_common.py
  46. +5 −5 misoclib/mem/sdram/test/lasmicon_df_tb.py → misoc/cores/lasmicon/test_df.py
  47. +4 −4 misoclib/mem/sdram/test/lasmicon_tb.py → misoc/cores/lasmicon/test_lasmi.py
  48. +2 −2 misoclib/mem/sdram/test/refresher.py → misoc/cores/lasmicon/test_refresher.py
  49. +5 −5 misoclib/mem/sdram/test/lasmicon_wb.py → misoc/cores/lasmicon/test_wb.py
  50. 0 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/LICENSE
  51. 0 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/README
  52. 0 {misoclib/tools → misoc/cores/liteeth_mini}/__init__.py
  53. +6 −12 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/common.py
  54. +6 −3 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/mac/__init__.py
  55. +28 −28 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/mac/core/__init__.py
  56. +14 −8 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/mac/core/crc.py
  57. +20 −5 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/mac/core/gap.py
  58. +4 −1 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/mac/core/last_be.py
  59. +19 −7 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/mac/core/padding.py
  60. +7 −1 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/mac/core/preamble.py
  61. 0 {misoclib/mem/sdram/phy → misoc/cores/liteeth_mini/mac/frontend}/__init__.py
  62. +39 −21 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/mac/frontend/sram.py
  63. +7 −4 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/mac/frontend/wishbone.py
  64. +6 −10 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/phy/__init__.py
  65. +11 −11 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/phy/gmii.py
  66. +21 −12 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/phy/gmii_mii.py
  67. +8 −4 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/phy/loopback.py
  68. +17 −9 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/phy/mii.py
  69. +7 −8 {misoclib/com/liteethmini → misoc/cores/liteeth_mini}/phy/s6rgmii.py
  70. +1 −0 misoc/cores/lm32/__init__.py
  71. +7 −4 misoclib/cpu/lm32.py → misoc/cores/lm32/core.py
  72. 0 {extcores/lm32 → misoc/cores/lm32/verilog}/lm32_config.v
  73. 0 {extcores/lm32 → misoc/cores/lm32/verilog}/submodule
  74. +1 −0 misoc/cores/minicon/__init__.py
  75. +11 −14 misoclib/mem/sdram/core/minicon/__init__.py → misoc/cores/minicon/core.py
  76. +5 −5 misoclib/mem/sdram/test/minicon_tb.py → misoc/cores/minicon/test.py
  77. +1 −0 misoc/cores/mor1kx/__init__.py
  78. +7 −4 misoclib/cpu/mor1kx.py → misoc/cores/mor1kx/core.py
  79. +1 −0 misoc/cores/mor1kx/verilog
  80. 0 {misoclib → misoc/cores}/mxcrg.v
  81. +3 −2 misoclib/mem/flash/norflash16.py → misoc/cores/nor_flash_16.py
  82. +3 −4 misoclib/mem/sdram/phy/simphy.py → misoc/cores/sdram_model.py
  83. +3 −0 misoc/cores/sdram_phy/__init__.py
  84. +10 −11 {misoclib/mem/sdram/phy → misoc/cores/sdram_phy}/gensdrphy.py
  85. +10 −11 {misoclib/mem/sdram/phy → misoc/cores/sdram_phy}/k7ddrphy.py
  86. +25 −28 {misoclib/mem/sdram/phy → misoc/cores/sdram_phy}/s6ddrphy.py
  87. +22 −17 misoclib/mem/sdram/module.py → misoc/cores/sdram_settings.py
  88. +14 −10 misoclib/mem/sdram/frontend/memtest.py → misoc/cores/sdram_tester.py
  89. +1 −0 misoc/cores/spi/__init__.py
  90. +2 −4 misoclib/com/spi/__init__.py → misoc/cores/spi/core.py
  91. +2 −2 misoclib/com/spi/test/spi_master_tb.py → misoc/cores/spi/test.py
  92. +7 −44 misoclib/mem/flash/spiflash.py → misoc/cores/spi_flash.py
  93. +4 −3 {misoclib/cpu → misoc/cores}/timer.py
  94. +1 −0 misoc/cores/uart/__init__.py
  95. +68 −10 misoclib/com/uart/phy/serial.py → misoc/cores/uart/core.py
  96. 0 misoclib/com/uart/test/test_serial_phy.py → misoc/cores/uart/test.py
  97. +2 −0 misoc/integration/__init__.py
  98. +168 −0 misoc/integration/builder.py
  99. +13 −7 misoclib/soc/cpuif.py → misoc/integration/cpu_interface.py
  100. +1 −1 misoclib/mem/sdram/phy/initsequence.py → misoc/integration/sdram_init.py
  101. +211 −0 misoc/integration/soc_core.py
  102. +121 −0 misoc/integration/soc_sdram.py
  103. 0 {misoclib/mem/sdram/frontend → misoc/interconnect}/__init__.py
  104. +147 −0 misoc/interconnect/csr.py
  105. +184 −0 misoc/interconnect/csr_bus.py
  106. +86 −0 misoc/interconnect/csr_eventmanager.py
  107. +1 −1 {misoclib/mem/sdram/phy → misoc/interconnect}/dfi.py
  108. +1 −2 {misoclib/mem/sdram/frontend → misoc/interconnect}/dma_lasmi.py
  109. +35 −5 misoclib/mem/sdram/core/lasmixbar.py → misoc/interconnect/lasmi_bus.py
  110. +387 −0 misoc/interconnect/stream.py
  111. +671 −0 misoc/interconnect/wishbone.py
  112. +28 −0 misoc/interconnect/wishbone2csr.py
  113. +2 −1 {misoclib/mem/sdram/frontend → misoc/interconnect}/wishbone2lasmi.py
  114. +37 −0 misoc/software/bios/Makefile
  115. 0 { → misoc}/software/bios/boot-helper-lm32.S
  116. 0 { → misoc}/software/bios/boot-helper-or1k.S
  117. +2 −2 { → misoc}/software/bios/boot.c
  118. 0 { → misoc}/software/bios/boot.h
  119. 0 {software/memtest → misoc/software/bios}/isr.c
  120. 0 { → misoc}/software/bios/linker.ld
  121. +16 −30 { → misoc}/software/bios/main.c
  122. 0 { → misoc}/software/bios/sdram.c
  123. 0 { → misoc}/software/bios/sdram.h
  124. 0 {common → misoc/software/bios}/sfl.h
  125. +9 −24 { → misoc}/software/common.mak
  126. +1 −0 misoc/software/compiler_rt
  127. 0 { → misoc}/software/include/base/assert.h
  128. 0 { → misoc}/software/include/base/console.h
  129. 0 { → misoc}/software/include/base/crc.h
  130. 0 { → misoc}/software/include/base/ctype.h
  131. 0 { → misoc}/software/include/base/endian.h
  132. 0 { → misoc}/software/include/base/errno.h
  133. 0 { → misoc}/software/include/base/float.h
  134. +2 −2 { → misoc}/software/include/base/id.h
  135. 0 { → misoc}/software/include/base/inttypes.h
  136. 0 { → misoc}/software/include/base/irq.h
  137. 0 { → misoc}/software/include/base/limits.h
  138. 0 { → misoc}/software/include/base/pthread.h
  139. 0 { → misoc}/software/include/base/spiflash.h
  140. 0 { → misoc}/software/include/base/spr-defs.h
  141. 0 { → misoc}/software/include/base/stdarg.h
  142. 0 { → misoc}/software/include/base/stdbool.h
  143. 0 { → misoc}/software/include/base/stddef.h
  144. 0 { → misoc}/software/include/base/stdint.h
  145. 0 { → misoc}/software/include/base/stdio.h
  146. 0 { → misoc}/software/include/base/stdlib.h
  147. 0 { → misoc}/software/include/base/string.h
  148. 0 { → misoc}/software/include/base/system.h
  149. 0 { → misoc}/software/include/base/time.h
  150. 0 { → misoc}/software/include/base/uart.h
  151. 0 { → misoc}/software/include/basec++/algorithm
  152. 0 { → misoc}/software/include/basec++/cstddef
  153. 0 { → misoc}/software/include/basec++/cstdlib
  154. 0 { → misoc}/software/include/basec++/new
  155. 0 { → misoc}/software/include/dyld/dlfcn.h
  156. 0 { → misoc}/software/include/dyld/dyld.h
  157. 0 { → misoc}/software/include/dyld/elf.h
  158. 0 { → misoc}/software/include/dyld/link.h
  159. 0 { → misoc}/software/include/hw/common.h
  160. 0 { → misoc}/software/include/hw/ethmac_mem.h
  161. 0 { → misoc}/software/include/hw/flags.h
  162. 0 { → misoc}/software/include/net/microudp.h
  163. 0 { → misoc}/software/include/net/tftp.h
  164. +9 −12 { → misoc}/software/libbase/Makefile
  165. 0 { → misoc}/software/libbase/console.c
  166. 0 { → misoc}/software/libbase/crc16.c
  167. 0 { → misoc}/software/libbase/crc32.c
  168. 0 { → misoc}/software/libbase/crt0-lm32.S
  169. 0 { → misoc}/software/libbase/crt0-or1k.S
  170. 0 { → misoc}/software/libbase/errno.c
  171. 0 { → misoc}/software/libbase/exception.c
  172. +20 −0 misoc/software/libbase/id.c
  173. 0 { → misoc}/software/libbase/libc.c
  174. 0 { → misoc}/software/libbase/linker-sdram.ld
  175. 0 { → misoc}/software/libbase/qsort.c
  176. 0 { → misoc}/software/libbase/spiflash.c
  177. 0 { → misoc}/software/libbase/strtod.c
  178. 0 { → misoc}/software/libbase/system.c
  179. +1 −1 { → misoc}/software/libbase/time.c
  180. 0 { → misoc}/software/libbase/uart.c
  181. 0 { → misoc}/software/libbase/vsnprintf.c
  182. +21 −0 misoc/software/libcompiler_rt/Makefile
  183. +26 −0 misoc/software/libdyld/Makefile
  184. 0 { → misoc}/software/libdyld/dyld.c
  185. +20 −0 misoc/software/libnet/Makefile
  186. +1 −1 { → misoc}/software/libnet/microudp.c
  187. 0 { → misoc}/software/libnet/tftp.c
  188. +35 −0 misoc/software/libunwind/Makefile
  189. 0 { → misoc}/software/libunwind/__cxxabi_config.h
  190. +3 −6 { → misoc}/software/memtest/Makefile
  191. 0 {software/bios → misoc/software/memtest}/isr.c
  192. +3 −5 { → misoc}/software/memtest/main.c
  193. +1 −0 misoc/software/unwinder
  194. 0 {misoclib/mem/flash → misoc/targets}/__init__.py
  195. +31 −15 { → misoc}/targets/de0nano.py
  196. +57 −22 { → misoc}/targets/kc705.py
  197. +137 −0 misoc/targets/mimasv2.py
  198. +32 −16 { → misoc}/targets/minispartan6.py
  199. +64 −31 { → misoc}/targets/mlabs_video.py
  200. +35 −19 targets/ppro.py → misoc/targets/papilio_pro.py
  201. +44 −23 { → misoc}/targets/pipistrello.py
  202. +33 −8 { → misoc}/targets/simple.py
  203. 0 {misoclib/mem → misoc/tools}/__init__.py
  204. +8 −4 { → misoc}/tools/flterm.py
  205. +36 −0 misoc/tools/mkmscimg.py
  206. +0 −17 misoc_import.py
  207. 0 misoclib/__init__.py
  208. 0 misoclib/com/__init__.py
  209. 0 misoclib/com/liteethmini/__init__.py
  210. 0 misoclib/com/liteethmini/mac/frontend/__init__.py
  211. +0 −58 misoclib/com/liteethmini/phy/sim.py
  212. +0 −58 misoclib/com/uart/__init__.py
  213. +0 −9 misoclib/com/uart/bridge.py
  214. +0 −8 misoclib/com/uart/phy/__init__.py
  215. +0 −33 misoclib/com/uart/phy/sim.py
  216. 0 misoclib/com/uart/software/__init__.py
  217. +0 −55 misoclib/com/uart/software/reg.py
  218. +0 −75 misoclib/com/uart/software/wishbone.py
  219. 0 misoclib/cpu/__init__.py
  220. +0 −26 misoclib/cpu/identifier.py
  221. +0 −11 misoclib/mem/sdram/__init__.py
  222. +0 −36 misoclib/mem/sdram/core/__init__.py
  223. +0 −164 misoclib/mem/sdram/core/lasmibus.py
  224. +0 −70 misoclib/mem/sdram/core/lasmicon/refresher.py
  225. +0 −42 misoclib/mem/sdram/test/abstract_transactions_lasmi.py
  226. +0 −204 misoclib/soc/__init__.py
  227. +0 −111 misoclib/soc/sdram.py
  228. +0 −149 misoclib/tools/wishbone.py
  229. +0 −12 mkmscimg.py
  230. +41 −38 setup.py
  231. +0 −45 software/bios/Makefile
  232. +0 −42 software/bios/dataflow.c
  233. +0 −7 software/bios/dataflow.h
  234. +0 −1 software/compiler-rt
  235. 0 software/include/generated/.keep_me
  236. +0 −20 software/libbase/id.c
  237. +0 −24 software/libcompiler-rt/Makefile
  238. +0 −19 software/libdyld/Makefile
  239. +0 −23 software/libnet/Makefile
  240. +0 −30 software/libunwind/Makefile
  241. +0 −1 software/unwinder
  242. +0 −18 targets/versa.py
  243. +0 −18 tools/Makefile
  244. +0 −60 tools/byteswap.c
  245. +0 −793 tools/flterm.c
14 changes: 2 additions & 12 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -1,15 +1,5 @@
__pycache__
build/*
*.o
*.d
*.a
*.elf
*.bin
*.fbi
tools/flterm
tools/byteswap
software/include/generated/*.h
software/include/generated/*.ld
software/include/generated/*.mak
*.pyc
*.egg-info
*.vcd
outgoing
20 changes: 10 additions & 10 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
[submodule "extcores/lm32/submodule"]
path = extcores/lm32/submodule
[submodule "misoc/cores/lm32/verilog/submodule"]
path = misoc/cores/lm32/verilog/submodule
url = https://github.com/m-labs/lm32.git
[submodule "extcores/mor1kx/submodule"]
path = extcores/mor1kx/submodule
url = https://github.com/openrisc/mor1kx.git
[submodule "software/compiler-rt"]
path = software/compiler-rt
[submodule "misoc/cores/mor1kx/verilog"]
path = misoc/cores/mor1kx/verilog
url = https://github.com/openrisc/mor1kx.git
[submodule "misoc/software/compiler_rt"]
path = misoc/software/compiler_rt
url = http://llvm.org/git/compiler-rt.git
[submodule "software/unwinder"]
path = software/unwinder
url = https://github.com/whitequark/libunwind
[submodule "misoc/software/unwinder"]
path = misoc/software/unwinder
url = http://llvm.org/git/libunwind.git
36 changes: 36 additions & 0 deletions .travis.yml
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@@ -0,0 +1,36 @@
language: python
python:
- "3.5"

env:
global:
- PATH=$HOME/miniconda/bin:$PATH

before_install:
# Install Miniconda
- wget https://raw.githubusercontent.com/m-labs/artiq/master/.travis/get-anaconda.sh
- chmod +x get-anaconda.sh
- ./get-anaconda.sh
- source $HOME/miniconda/bin/activate py35
- conda install anaconda-client
install:
# workaround for https://github.com/conda/conda-build/issues/466
- "mkdir -p /home/travis/miniconda/conda-bld/linux-64"
- "conda index /home/travis/miniconda/conda-bld/linux-64"
- "conda build --python 3.5 conda/misoc"
- "conda install $(conda build --output --python 3.5 conda/misoc)"
script:
- true

after_success:
- if [ "${TRAVIS_PULL_REQUEST}" = "false" ]; then anaconda login --hostname $(hostname) --username $binstar_login --password $binstar_password; fi
- if [ "${TRAVIS_PULL_REQUEST}" = "false" ]; then anaconda upload --user $binstar_login --channel dev --force $HOME/miniconda/conda-bld/noarch/misoc-*.tar.bz2; fi

notifications:
email: false
irc:
channels:
- chat.freenode.net#m-labs
template:
- "%{repository}#%{build_number} (%{branch} - %{commit} : %{author}): %{message}"
- "Build details : %{build_url}"
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4 changes: 4 additions & 0 deletions MANIFEST.in
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@@ -0,0 +1,4 @@
graft misoc/software
graft misoc/cores/lm32/verilog
graft misoc/cores/mor1kx/verilog
include misoc/cores/mxcrg.v
2 changes: 1 addition & 1 deletion README
Original file line number Diff line number Diff line change
@@ -106,7 +106,7 @@ modules.

9. Contribute a patch!
Once you have experimented with stuff, please send your results back.
For more details on how to do so, you can see the CONTRIBUTING.md file.
For more details on how to do so, you can see the CONTRIBUTING.rst file.

[> License
----------
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1 change: 1 addition & 0 deletions conda/misoc/bld.bat
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@@ -0,0 +1 @@
%PYTHON% setup.py install
26 changes: 26 additions & 0 deletions conda/misoc/meta.yaml
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@@ -0,0 +1,26 @@
package:
name: misoc
version: {{ environ.get("GIT_DESCRIBE_TAG", "") }}

source:
git_url: https://github.com/m-labs/misoc
git_tag: master

build:
noarch_python: true
number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_DESCRIBE_HASH", "")[1:] }}
script: $PYTHON setup.py install

requirements:
build:
- migen
- python
run:
- migen
- python

about:
home: http://m-labs.hk/gateware.html
license: 3-clause BSD
summary: 'A high performance and small footprint SoC based on Migen'
20 changes: 0 additions & 20 deletions crc.py

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1 change: 0 additions & 1 deletion extcores/mor1kx/submodule
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32 changes: 0 additions & 32 deletions flash_extra.py

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222 changes: 0 additions & 222 deletions make.py

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