csr read/write needs an extra cycle

m-labs · Nov 17, 2015 · 6869f09 · 6869f09
1 parent 029bd6c
commit 6869f09
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/misoc/interconnect/csr_bus.py b/misoc/interconnect/csr_bus.py
@@ -30,6 +30,7 @@ def write(self, adr, dat):
     def read(self, adr):
         yield self.adr.eq(adr)
         yield
+        yield
         return (yield self.dat_r)