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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: e893f56aff96
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Nov 15, 2015

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    1846258 View commit details
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    e893f56 View commit details
Showing with 47 additions and 40 deletions.
  1. +5 −11 migen/sim/core.py
  2. +42 −29 migen/sim/vcd.py
16 changes: 5 additions & 11 deletions migen/sim/core.py
Original file line number Diff line number Diff line change
@@ -8,7 +8,7 @@
_Operator, _Slice, _ArrayProxy,
_Assign, _Fragment)
from migen.fhdl.bitcontainer import value_bits_sign
from migen.fhdl.tools import list_signals, list_targets, insert_resets
from migen.fhdl.tools import list_targets, insert_resets
from migen.fhdl.simplify import MemoryToArray
from migen.fhdl.specials import _MemoryLocation
from migen.sim.vcd import VCDWriter, DummyVCDWriter
@@ -23,7 +23,7 @@ def __init__(self, high, half_period, time_before_trans):

class TimeManager:
def __init__(self, description):
self.clocks = dict()
self.clocks = collections.OrderedDict()

for k, period_phase in description.items():
if isinstance(period_phase, tuple):
@@ -229,6 +229,8 @@ def __init__(self, fragment_or_module, generators, clocks={"sys": 10}, vcd_name=
else:
self.generators[k] = [v]

clocks = collections.OrderedDict(sorted(clocks.items(),
key=operator.itemgetter(0)))
self.time = TimeManager(clocks)
for clock in clocks.keys():
if clock not in self.fragment.clock_domains:
@@ -248,15 +250,7 @@ def __init__(self, fragment_or_module, generators, clocks={"sys": 10}, vcd_name=
if vcd_name is None:
self.vcd = DummyVCDWriter()
else:
signals = list_signals(self.fragment)
for cd in self.fragment.clock_domains:
signals.add(cd.clk)
if cd.rst is not None:
signals.add(cd.rst)
for memory_array in mta.replacements.values():
signals |= set(memory_array)
signals = sorted(signals, key=lambda x: x.duid)
self.vcd = VCDWriter(vcd_name, signals)
self.vcd = VCDWriter(vcd_name)

def __enter__(self):
return self
71 changes: 42 additions & 29 deletions migen/sim/vcd.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,8 @@
from itertools import count
import tempfile
import os
from collections import OrderedDict
import shutil

from migen.fhdl.namer import build_namespace

@@ -15,53 +19,62 @@ def vcd_codes():


class VCDWriter:
def __init__(self, filename, signals):
self.fo = open(filename, "w")
self.codes = dict()
def __init__(self, filename):
self.filename = filename
self.buffer_file = tempfile.TemporaryFile(
dir=os.path.dirname(filename), mode="w+")
self.codegen = vcd_codes()
self.codes = OrderedDict()
self.signal_values = dict()
self.t = 0

try:
ns = build_namespace(signals)
codes = vcd_codes()
for signal in signals:
name = ns.get_name(signal)
code = next(codes)
self.codes[signal] = code
self.fo.write("$var wire {len} {code} {name} $end\n"
.format(name=name, code=code, len=len(signal)))
self.fo.write("$dumpvars\n")
for signal in signals:
value = signal.reset.value
self._write_value(signal, value)
self.signal_values[signal] = value
self.fo.write("$end\n")
self.fo.write("#0\n")
except:
self.close()
raise

def _write_value(self, signal, value):
def _write_value(self, f, signal, value):
l = len(signal)
if value < 0:
value += 2**l
if l > 1:
fmtstr = "b{:0" + str(l) + "b} {}\n"
else:
fmtstr = "{}{}\n"
self.fo.write(fmtstr.format(value, self.codes[signal]))
try:
code = self.codes[signal]
except KeyError:
code = next(self.codegen)
self.codes[signal] = code
f.write(fmtstr.format(value, code))

def set(self, signal, value):
if self.signal_values[signal] != value:
self._write_value(signal, value)
if signal in self.signal_values:
write = self.signal_values[signal] != value
else:
write = signal.reset.value != value
if write:
self._write_value(self.buffer_file, signal, value)
self.signal_values[signal] = value

def delay(self, delay):
self.t += delay
self.fo.write("#{}\n".format(self.t))
self.buffer_file.write("#{}\n".format(self.t))

def close(self):
self.fo.close()
out = open(self.filename, "w")
try:
ns = build_namespace(self.codes.keys())
for signal, code in self.codes.items():
name = ns.get_name(signal)
out.write("$var wire {len} {code} {name} $end\n"
.format(name=name, code=code, len=len(signal)))
out.write("$dumpvars\n")
for signal in self.codes.keys():
self._write_value(out, signal, signal.reset.value)
out.write("$end\n")
out.write("#0\n")

self.buffer_file.seek(0)
shutil.copyfileobj(self.buffer_file, out)
self.buffer_file.close()
finally:
out.close()


class DummyVCDWriter: