Add ARTIQ_DUMP_ASSEMBLY.

m-labs · Aug 9, 2015 · 8b7d38d · 8b7d38d
1 parent 9c5ca2a
commit 8b7d38d
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Showing 2 changed files with 21 additions and 11 deletions.
diff --git a/artiq/compiler/targets.py b/artiq/compiler/targets.py
@@ -1,4 +1,4 @@
-import tempfile, subprocess
+import os, sys, tempfile, subprocess
 from llvmlite_artiq import ir as ll, binding as llvm
 
 llvm.initialize()
@@ -56,10 +56,20 @@ def make_tempfile(data=b""):
 
     def compile(self, module):
         """Compile the module to a relocatable object for this target."""
+
+        if os.getenv('ARTIQ_DUMP_IR'):
+            print("====== ARTIQ IR DUMP ======", file=sys.stderr)
+            for function in module.artiq_ir:
+                print(function, file=sys.stderr)
+
         llmod = module.build_llvm_ir(self)
         llparsedmod = llvm.parse_assembly(str(llmod))
         llparsedmod.verify()
 
+        if os.getenv('ARTIQ_DUMP_LLVM'):
+            print("====== LLVM IR DUMP ======", file=sys.stderr)
+            print(str(llparsedmod), file=sys.stderr)
+
         llpassmgrbuilder = llvm.create_pass_manager_builder()
         llpassmgrbuilder.opt_level  = 2 # -O2
         llpassmgrbuilder.size_level = 1 # -Os
@@ -68,10 +78,19 @@ def compile(self, module):
         llpassmgrbuilder.populate(llpassmgr)
         llpassmgr.run(llparsedmod)
 
+        if os.getenv('ARTIQ_DUMP_LLVM'):
+            print("====== LLVM IR DUMP (OPTIMIZED) ======", file=sys.stderr)
+            print(str(llparsedmod), file=sys.stderr)
+
         lltarget = llvm.Target.from_triple(self.triple)
         llmachine = lltarget.create_target_machine(
                         features=",".join(self.features),
                         reloc="pic", codemodel="default")
+
+        if os.getenv('ARTIQ_DUMP_ASSEMBLY'):
+            print("====== ASSEMBLY DUMP ======", file=sys.stderr)
+            print(llmachine.emit_assembly(llparsedmod), file=sys.stderr)
+
         return llmachine.emit_object(llparsedmod)
 
     def compile_and_link(self, modules):

diff --git a/artiq/coredevice/core.py b/artiq/coredevice/core.py
@@ -1,4 +1,4 @@
-import os, sys, tempfile
+import sys, tempfile
 
 from pythonparser import diagnostic
 
@@ -35,15 +35,6 @@ def compile(self, function, args, kwargs, with_attr_writeback=True):
             module = Module(stitcher)
             target = OR1KTarget()
 
-            if os.getenv('ARTIQ_DUMP_IR'):
-                print("====== ARTIQ IR DUMP ======", file=sys.stderr)
-                for function in module.artiq_ir:
-                    print(function, file=sys.stderr)
-
-            if os.getenv('ARTIQ_DUMP_LLVM'):
-                print("====== LLVM IR DUMP ======", file=sys.stderr)
-                print(module.build_llvm_ir(target), file=sys.stderr)
-
             return target.compile_and_link([module]), stitcher.rpc_map
         except diagnostic.Error as error:
             print("\n".join(error.diagnostic.render(colored=True)), file=sys.stderr)