m-labs · Aug 8, 2015 · Aug 8, 2015 · Aug 8, 2015 · Aug 8, 2015
Showing with 50 additions and 26 deletions.

+5 −2 artiq/coredevice/dds.py

+6 −3 artiq/frontend/artiq_client.py

+19 −16 artiq/master/repository.py

+12 −0 artiq/tools.py

+8 −5 doc/manual/core_device.rst
diff --git a/artiq/coredevice/dds.py b/artiq/coredevice/dds.py
@@ -33,13 +33,16 @@ def __init__(self, dmgr):
     @kernel
     def batch_enter(self):
         """Starts a DDS command batch. All DDS commands are buffered
-        after this call, until ``batch_exit`` is called."""
+        after this call, until ``batch_exit`` is called.
+
+        The time of execution of the DDS commands is the time of entering the
+        batch (as closely as hardware permits)."""
         syscall("dds_batch_enter", now_mu())
 
     @kernel
     def batch_exit(self):
         """Ends a DDS command batch. All buffered DDS commands are issued
-        on the bus, and FUD is pulsed at the time the batch started."""
+        on the bus."""
         syscall("dds_batch_exit")
 
 

diff --git a/artiq/frontend/artiq_client.py b/artiq/frontend/artiq_client.py
@@ -87,8 +87,11 @@ def get_argparser():
         "what",
         help="select object to show: schedule/log/devices/parameters")
 
-    subparsers.add_parser("scan-repository",
-                          help="trigger a repository rescan")
+    parser_scan = subparsers.add_parser("scan-repository",
+                                        help="trigger a repository (re)scan")
+    parser_scan.add_argument("revision", default=None, nargs="?",
+                             help="use a specific repository revision "
+                                  "(defaults to head)")
 
     return parser
 
@@ -145,7 +148,7 @@ def _action_del_parameter(remote, args):
 
 
 def _action_scan_repository(remote, args):
-    remote.scan_async()
+    remote.scan_async(args.revision)
 
 
 def _show_schedule(schedule):

diff --git a/artiq/master/repository.py b/artiq/master/repository.py
@@ -6,6 +6,7 @@
 
 from artiq.protocols.sync_struct import Notifier
 from artiq.master.worker import Worker
+from artiq.tools import exc_to_warning
 
 
 logger = logging.getLogger(__name__)
@@ -57,33 +58,35 @@ def __init__(self, backend, log_fn):
         self.backend = backend
         self.log_fn = log_fn
 
-        self.head_rev = self.backend.get_head_rev()
-        self.backend.request_rev(self.head_rev)
+        self.cur_rev = self.backend.get_head_rev()
+        self.backend.request_rev(self.cur_rev)
         self.explist = Notifier(dict())
 
         self._scanning = False
 
     def close(self):
         # The object cannot be used anymore after calling this method.
-        self.backend.release_rev(self.head_rev)
+        self.backend.release_rev(self.cur_rev)
 
     @asyncio.coroutine
-    def scan(self):
+    def scan(self, new_cur_rev=None):
         if self._scanning:
             return
         self._scanning = True
-
-        new_head_rev = self.backend.get_head_rev()
-        wd, _ = self.backend.request_rev(new_head_rev)
-        self.backend.release_rev(self.head_rev)
-        self.head_rev = new_head_rev
-        new_explist = yield from _scan_experiments(wd, self.log_fn)
-
-        _sync_explist(self.explist, new_explist)
-        self._scanning = False
-
-    def scan_async(self):
-        asyncio.async(self.scan())
+        try:
+            if new_cur_rev is None:
+                new_cur_rev = self.backend.get_head_rev()
+            wd, _ = self.backend.request_rev(new_cur_rev)
+            self.backend.release_rev(self.cur_rev)
+            self.cur_rev = new_cur_rev
+            new_explist = yield from _scan_experiments(wd, self.log_fn)
+
+            _sync_explist(self.explist, new_explist)
+        finally:
+            self._scanning = False
+
+    def scan_async(self, new_cur_rev=None):
+        asyncio.async(exc_to_warning(self.scan(new_cur_rev)))
 
 
 class FilesystemBackend:

diff --git a/artiq/tools.py b/artiq/tools.py
@@ -11,6 +11,9 @@
 from artiq.protocols import pyon
 
 
+logger = logging.getLogger(__name__)
+
+
 def parse_arguments(arguments):
     d = {}
     for argument in arguments:
@@ -75,6 +78,15 @@ def init_logger(args):
     logging.basicConfig(level=logging.WARNING + args.quiet*10 - args.verbose*10)
 
 
+@asyncio.coroutine
+def exc_to_warning(coro):
+    try:
+        yield from coro
+    except:
+        logger.warning("asyncio coroutine terminated with exception",
+                       exc_info=True)
+
+
 @asyncio.coroutine
 def asyncio_process_wait_timeout(process, timeout):
     # In Python < 3.5, asyncio.wait_for(process.wait(), ...

diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst
@@ -1,20 +1,23 @@
 Core device
 ===========
 
+The core device is a FPGA-based hardware component that contains a softcore CPU tightly coupled with the so-called RTIO core that provides precision timing. The CPU executes Python code that is statically compiled by the ARTIQ compiler, and communicates with the core device peripherals (TTL, DDS, etc.) over the RTIO core. This architecture provides high timing resolution, low latency, low jitter, high level programming capabilities, and good integration with the rest of the Python experiment code.
+
+While it is possible to use all the other parts of ARTIQ (controllers, master, GUI, result management, etc.) without a core device, many experiments require it.
+
+
 .. _core-device-flash-storage:
 
 Flash storage
 *************
 
-The core device contains some flash space that can be used to store
-some configuration data.
+The core device contains some flash space that can be used to store configuration data.
 
 This storage area is used to store the core device MAC address, IP address and even the idle kernel.
 
-The flash storage area is one sector (typically 64 kB) large and is organized as a list
-of key-value records.
+The flash storage area is one sector (typically 64 kB) large and is organized as a list of key-value records.
 
-This flash storage space can be accessed by using the artiq_coretool :ref:`core-device-access-tool`.
+This flash storage space can be accessed by using ``artiq_coretool`` (see: :ref:`core-device-access-tool`).
 
 
 FPGA board ports