LLVMIRGenerator: fixup phis on expansion of ARTIQ instructions.

m-labs · Aug 9, 2015 · f7b64db · f7b64db
1 parent d4270cf
commit f7b64db
Showing 1 changed file with 9 additions and 1 deletion.
diff --git a/artiq/compiler/transforms/llvm_ir_generator.py b/artiq/compiler/transforms/llvm_ir_generator.py
@@ -17,6 +17,7 @@ def __init__(self, engine, module_name, target):
         self.llmodule.data_layout = target.data_layout
         self.llfunction = None
         self.llmap = {}
+        self.llblock_map = {}
         self.fixups = []
 
     def llty_of_type(self, typ, bare=False, for_return=False):
@@ -229,6 +230,13 @@ def process_function(self, func):
                     assert llinsn is not None
                     self.llmap[insn] = llinsn
 
+                # There is no 1:1 correspondence between ARTIQ and LLVM
+                # basic blocks, because sometimes we expand a single ARTIQ
+                # instruction so that the result spans several LLVM basic
+                # blocks. This only really matters for phis, which will
+                # use a different map.
+                self.llblock_map[block] = self.llbuilder.basic_block
+
             # Fourth, fixup phis.
             for fixup in self.fixups:
                 fixup()
@@ -241,7 +249,7 @@ def process_Phi(self, insn):
         llinsn = self.llbuilder.phi(self.llty_of_type(insn.type), name=insn.name)
         def fixup():
             for value, block in insn.incoming():
-                llinsn.add_incoming(self.map(value), self.map(block))
+                llinsn.add_incoming(self.map(value), self.llblock_map[block])
         self.fixups.append(fixup)
         return llinsn