Skip to content

Commit

Permalink
pack memory maps
Browse files Browse the repository at this point in the history
sbourdeauducq committed Dec 16, 2015
1 parent 17cfcbe commit 2aa4fb7
Showing 3 changed files with 7 additions and 8 deletions.
4 changes: 2 additions & 2 deletions misoc/integration/soc_sdram.py
Original file line number Diff line number Diff line change
@@ -12,8 +12,8 @@

class SoCSDRAM(SoCCore):
csr_map = {
"dfii": 8,
"l2_cache": 9
"dfii": 7,
"l2_cache": 8
}
csr_map.update(SoCCore.csr_map)

9 changes: 4 additions & 5 deletions misoc/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -16,7 +16,6 @@
from misoc.integration.builder import *



class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
@@ -78,8 +77,8 @@ class BaseSoC(SoCSDRAM):
default_platform = "kc705"

csr_map = {
"spiflash": 16,
"ddrphy": 17,
"spiflash": 9,
"ddrphy": 10,
}
csr_map.update(SoCSDRAM.csr_map)

@@ -111,8 +110,8 @@ def __init__(self, toolchain="ise", sdram_controller_type="minicon", **kwargs):

class MiniSoC(BaseSoC):
csr_map = {
"ethphy": 18,
"ethmac": 19,
"ethphy": 11,
"ethmac": 12,
}
csr_map.update(BaseSoC.csr_map)

2 changes: 1 addition & 1 deletion misoc/targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -96,7 +96,7 @@ def __init__(self, platform, clk_freq):

class BaseSoC(SoCSDRAM):
csr_map = {
"spiflash": 16,
"spiflash": 9,
}
csr_map.update(SoCSDRAM.csr_map)

0 comments on commit 2aa4fb7

Please sign in to comment.