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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 4def5617106d
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Dec 16, 2015

  1. rtio/analyzer: fix superficial mistakes

    @sbourdeauducq
    sbourdeauducq committed Dec 16, 2015
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    afaad27 View commit details

  2. targets: integrate RTIO analyzer

    @sbourdeauducq
    sbourdeauducq committed Dec 16, 2015
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    4def561 View commit details
Showing with 10 additions and 6 deletions.
  1. +2 −2 artiq/gateware/rtio/analyzer.py
  2. +5 −1 artiq/gateware/targets/kc705.py
  3. +3 −3 artiq/gateware/targets/pipistrello.py
4 changes: 2 additions & 2 deletions artiq/gateware/rtio/analyzer.py
View file
Original file line number Diff line number Diff line change
@@ -52,7 +52,7 @@ def __init__(self):

class MessageEncoder(Module, AutoCSR):
def __init__(self, rtio_core):
self.source = stream.Endpoint("data", 256)
self.source = stream.Endpoint([("data", 256)])

self.message_types = MessageTypes()
self.exception_types = ExceptionTypes()
@@ -75,7 +75,7 @@ def __init__(self, rtio_core):
else:
o_address = 0
if hasattr(kcsrs, "i_data"):
i_data = kcsrs.i_data
i_data = kcsrs.i_data.status
else:
i_data = 0
self.comb += [
6 changes: 5 additions & 1 deletion artiq/gateware/targets/kc705.py
View file
Original file line number Diff line number Diff line change
@@ -85,7 +85,8 @@ class _NIST_QCx(MiniSoC, AMPSoC):
"rtio": None, # mapped on Wishbone instead
"rtio_crg": 13,
"kernel_cpu": 14,
"rtio_moninj": 15
"rtio_moninj": 15,
"rtio_analyzer": 16
}
csr_map.update(MiniSoC.csr_map)
mem_map = {
@@ -138,6 +139,9 @@ def add_rtio(self, rtio_channels):
self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
rtio_csrs)

self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
self.get_native_sdram_if())


class NIST_QC1(_NIST_QCx):
def __init__(self, cpu_type="or1k", **kwargs):
6 changes: 3 additions & 3 deletions artiq/gateware/targets/pipistrello.py
View file
Original file line number Diff line number Diff line change
@@ -104,9 +104,9 @@ def __init__(self, platform, clk_freq):
class NIST_QC1(BaseSoC, AMPSoC):
csr_map = {
"rtio": None, # mapped on Wishbone instead
"rtio_crg": 13,
"kernel_cpu": 14,
"rtio_moninj": 15
"rtio_crg": 10,
"kernel_cpu": 11,
"rtio_moninj": 12
}
csr_map.update(BaseSoC.csr_map)
mem_map = {