gateware/rtio/analyzer: fix bus write

m-labs · Dec 18, 2015 · 59a3ea4 · 59a3ea4
1 parent f431add
commit 59a3ea4
Showing 1 changed file with 5 additions and 3 deletions.
diff --git a/artiq/gateware/rtio/analyzer.py b/artiq/gateware/rtio/analyzer.py
@@ -187,11 +187,8 @@ def __init__(self, membus):
         )
         fsm.act("WRITE",
             self.busy.status.eq(1),
-
             membus.cyc.eq(1),
             membus.stb.eq(1),
-            membus.we.eq(1),
-            membus.sel.eq(2**len(membus.sel)-1),
 
             If(membus.ack,
                 If(membus.adr == self.last_address.storage,
@@ -204,6 +201,11 @@ def __init__(self, membus):
                 NextState("IDLE")
             )
         )
+        self.comb += [
+            membus.we.eq(1),
+            membus.sel.eq(2**len(membus.sel)-1),
+            membus.dat_w.eq(self.sink.data)
+        ]
 
 
 class Analyzer(Module, AutoCSR):