gateware/soc: use new SDRAM API call

m-labs · Dec 16, 2015 · 3386082 · 3386082
1 parent 35acc33
commit 3386082
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/artiq/gateware/soc.py b/artiq/gateware/soc.py
@@ -20,7 +20,7 @@ def __init__(self):
         self.submodules.timer0 = timer.Timer(width=64)
 
         self.submodules.kernel_cpu = amp.KernelCPU(self.platform)
-        self.add_wb_sdram_if(self.kernel_cpu.wb_sdram)
+        self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
 
         self.submodules.mailbox = amp.Mailbox()
         self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),