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Refactor SDRAM integration
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Support multiple native Wishbone interfaces on Minicon
SDRAM auto-disable when integrated_main_ram_size != 0 is not supported anymore, targets must define multiple sub-targets with and without SDRAM instead.
sbourdeauducq committed Dec 16, 2015
1 parent 4ec8f35 commit fddf0f2
Showing 17 changed files with 217 additions and 192 deletions.
6 changes: 1 addition & 5 deletions misoc/cores/lasmicon/core.py
Original file line number Diff line number Diff line change
@@ -7,11 +7,10 @@


class ControllerSettings:
def __init__(self, req_queue_size=8, read_time=32, write_time=16, with_bandwidth=False):
def __init__(self, req_queue_size=8, read_time=32, write_time=16):
self.req_queue_size = req_queue_size
self.read_time = read_time
self.write_time = write_time
self.with_bandwidth = with_bandwidth


class LASMIcon(Module):
@@ -48,6 +47,3 @@ def __init__(self, phy_settings, geom_settings, timing_settings,
self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings, controller_settings,
self.bank_machines, self.refresher,
self.dfi, self.lasmic)

def get_csrs(self):
return self.multiplexer.get_csrs()
8 changes: 1 addition & 7 deletions misoc/cores/lasmicon/multiplexer.py
Original file line number Diff line number Diff line change
@@ -5,7 +5,6 @@
from migen.genlib.roundrobin import *
from migen.genlib.fsm import FSM, NextState

from misoc.cores.lasmicon.perf import Bandwidth
from misoc.interconnect.csr import AutoCSR


@@ -96,8 +95,7 @@ def stb_and(cmd, attr):


class Multiplexer(Module, AutoCSR):
def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, bank_machines, refresher, dfi, lasmic,
with_bandwidth=False):
def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, bank_machines, refresher, dfi, lasmic):
assert(phy_settings.nphases == len(dfi.phases))
self.phy_settings = phy_settings

@@ -216,7 +214,3 @@ def steerer_sel(steerer, phy_settings, r_w_n):
)
fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases
fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)

if controller_settings.with_bandwidth:
data_width = phy_settings.dfi_databits*phy_settings.nphases
self.submodules.bandwidth = Bandwidth(self.choose_req.cmd, data_width)
5 changes: 3 additions & 2 deletions misoc/cores/lasmicon/perf.py
Original file line number Diff line number Diff line change
@@ -4,14 +4,15 @@


class Bandwidth(Module, AutoCSR):
def __init__(self, cmd, data_width, period_bits=24):
def __init__(self, lasmicon, period_bits=24):
self._update = CSR()
self._nreads = CSRStatus(period_bits)
self._nwrites = CSRStatus(period_bits)
self._data_width = CSRStatus(bits_for(data_width), reset=data_width)

###

cmd = lasmicon.multiplexer.choose_req.cmd

cmd_stb = Signal()
cmd_ack = Signal()
cmd_is_read = Signal()
40 changes: 20 additions & 20 deletions misoc/integration/sdram_init.py
Original file line number Diff line number Diff line change
@@ -15,18 +15,18 @@ def get_sdram_phy_header(sdram_phy_settings):
r += """
static void command_p{n}(int cmd)
{{
sdram_dfii_pi{n}_command_write(cmd);
sdram_dfii_pi{n}_command_issue_write(1);
dfii_pi{n}_command_write(cmd);
dfii_pi{n}_command_issue_write(1);
}}""".format(n=str(n))
r += "\n\n"

# rd/wr access macros
r += """
#define sdram_dfii_pird_address_write(X) sdram_dfii_pi{rdphase}_address_write(X)
#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi{wrphase}_address_write(X)
#define dfii_pird_address_write(X) dfii_pi{rdphase}_address_write(X)
#define dfii_piwr_address_write(X) dfii_pi{wrphase}_address_write(X)
#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi{rdphase}_baddress_write(X)
#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi{wrphase}_baddress_write(X)
#define dfii_pird_baddress_write(X) dfii_pi{rdphase}_baddress_write(X)
#define dfii_piwr_baddress_write(X) dfii_pi{wrphase}_baddress_write(X)
#define command_prd(X) command_p{rdphase}(X)
#define command_pwr(X) command_p{wrphase}(X)
@@ -36,24 +36,24 @@ def get_sdram_phy_header(sdram_phy_settings):
#
# sdrrd/sdrwr functions utilities
#
r += "#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE\n"
sdram_dfii_pix_wrdata_addr = []
r += "#define DFII_PIX_DATA_SIZE CSR_DFII_PI0_WRDATA_SIZE\n"
dfii_pix_wrdata_addr = []
for n in range(nphases):
sdram_dfii_pix_wrdata_addr.append("CSR_SDRAM_DFII_PI{n}_WRDATA_ADDR".format(n=n))
dfii_pix_wrdata_addr.append("CSR_DFII_PI{n}_WRDATA_ADDR".format(n=n))
r += """
const unsigned int sdram_dfii_pix_wrdata_addr[{n}] = {{
{sdram_dfii_pix_wrdata_addr}
const unsigned int dfii_pix_wrdata_addr[{n}] = {{
{dfii_pix_wrdata_addr}
}};
""".format(n=nphases, sdram_dfii_pix_wrdata_addr=",\n\t".join(sdram_dfii_pix_wrdata_addr))
""".format(n=nphases, dfii_pix_wrdata_addr=",\n\t".join(dfii_pix_wrdata_addr))

sdram_dfii_pix_rddata_addr = []
dfii_pix_rddata_addr = []
for n in range(nphases):
sdram_dfii_pix_rddata_addr.append("CSR_SDRAM_DFII_PI{n}_RDDATA_ADDR".format(n=n))
dfii_pix_rddata_addr.append("CSR_DFII_PI{n}_RDDATA_ADDR".format(n=n))
r += """
const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
{sdram_dfii_pix_rddata_addr}
const unsigned int dfii_pix_rddata_addr[{n}] = {{
{dfii_pix_rddata_addr}
}};
""".format(n=nphases, sdram_dfii_pix_rddata_addr=",\n\t".join(sdram_dfii_pix_rddata_addr))
""".format(n=nphases, dfii_pix_rddata_addr=",\n\t".join(dfii_pix_rddata_addr))
r += "\n"

# init sequence
@@ -213,10 +213,10 @@ def format_mr2(cwl, rtt_wr):
r += "static void init_sequence(void)\n{\n"
for comment, a, ba, cmd, delay in init_sequence:
r += "\t/* {0} */\n".format(comment)
r += "\tsdram_dfii_pi0_address_write({0:#x});\n".format(a)
r += "\tsdram_dfii_pi0_baddress_write({0:d});\n".format(ba)
r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
if cmd[:12] == "DFII_CONTROL":
r += "\tsdram_dfii_control_write({0});\n".format(cmd)
r += "\tdfii_control_write({0});\n".format(cmd)
else:
r += "\tcommand_p0({0});\n".format(cmd)
if delay:
2 changes: 1 addition & 1 deletion misoc/integration/soc_core.py
Original file line number Diff line number Diff line change
@@ -38,7 +38,7 @@ def __init__(self, platform, clk_freq,
cpu_type="lm32", cpu_reset_address=0x00000000,
integrated_rom_size=0,
integrated_sram_size=4096,
integrated_main_ram_size=0,
integrated_main_ram_size=16*1024,
shadow_base=0x80000000,
csr_data_width=8, csr_address_width=14,
with_uart=True, uart_baudrate=115200,
153 changes: 97 additions & 56 deletions misoc/integration/soc_sdram.py
Original file line number Diff line number Diff line change
@@ -10,75 +10,84 @@
__all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]


class ControllerInjector(Module, AutoCSR):
def __init__(self, phy, controller_type, geom_settings, timing_settings):
self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits,
phy.settings.dfi_databits, phy.settings.nphases)
self.comb += self.dfii.master.connect(phy.dfi)

if controller_type == "lasmicon":
self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings,
geom_settings,
timing_settings)
self.comb += controller.dfi.connect(self.dfii.slave)

self.submodules.crossbar = lasmi_bus.LASMIxbar([controller.lasmic],
controller.nrowbits)
elif controller_type == "minicon":
self.submodules.controller = controller = minicon.Minicon(phy.settings,
geom_settings,
timing_settings)
self.comb += controller.dfi.connect(self.dfii.slave)
else:
raise ValueError("Unsupported SDRAM controller type")


class SoCSDRAM(SoCCore):
csr_map = {
"sdram": 8,
"l2_cache": 9
"dfii": 8,
"l2_cache": 9
}
csr_map.update(SoCCore.csr_map)

def __init__(self, platform, clk_freq, l2_size=8192, **kwargs):
SoCCore.__init__(self, platform, clk_freq, **kwargs)
SoCCore.__init__(self, platform, clk_freq,
integrated_main_ram_size=0, **kwargs)

if l2_size:
self.config["L2_SIZE"] = l2_size
self.l2_size = l2_size

self._sdram_phy = []
self._wb_sdram_ifs = []
self._wb_sdram = wishbone.Interface()
self._cpulevel_sdram_ifs = []
self._cpulevel_sdram_if_arbitrated = wishbone.Interface()

def add_cpulevel_sdram_if(self, interface):
"""Registers a 32-bit Wishbone interface, capable of accessing SDRAM,
at the same level as the CPU.
def add_wb_sdram_if(self, interface):
This can be called anytime until finalization.
"""
if self.finalized:
raise FinalizeError
self._wb_sdram_ifs.append(interface)
self._cpulevel_sdram_ifs.append(interface)

def get_native_sdram_if(self):
"""Creates and registers a native SDRAM interface, tightly coupled to
the controller.
This can only be called after ``register_sdram``.
"""
if isinstance(self.sdram_controller, minicon.Minicon):
bus = wishbone.Interface(len(self.sdram_controller.bus.dat_w))
self._native_sdram_ifs.append(bus)
return bus
elif isinstance(self.sdram_controller, lasmicon.LASMIcon):
return self.sdram_controller.crossbar.get_master()
else:
raise TypeError

def register_sdram(self, phy, sdram_controller_type, geom_settings, timing_settings):
# register PHY
assert not self._sdram_phy
self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning

self.submodules.sdram = ControllerInjector(
phy, sdram_controller_type, geom_settings, timing_settings)

# connect CPU to SDRAM, needs to be done here so that we know the size
dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2
sdram_width = phy.settings.dfi_databits//dfi_databits_divisor
main_ram_size = 2**(geom_settings.bankbits +
geom_settings.rowbits +
geom_settings.colbits)*sdram_width//8
# XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories.
# TODO: modify mem_map to allow larger memories.
main_ram_size = min(main_ram_size, 256*1024*1024)
if self.l2_size:
self.config["L2_SIZE"] = self.l2_size

# add a Wishbone interface to the DRAM
wb_sdram = wishbone.Interface()
self.add_wb_sdram_if(wb_sdram)
self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)
self.add_cpulevel_sdram_if(wb_sdram)
self.register_mem("main_ram", self.mem_map["main_ram"],
wb_sdram, main_ram_size)

# create DFI injector
self.submodules.dfii = dfii.DFIInjector(
geom_settings.addressbits, geom_settings.bankbits,
phy.settings.dfi_databits, phy.settings.nphases)
self.comb += self.dfii.master.connect(phy.dfi)

# create controller
if sdram_controller_type == "minicon":
self.submodules.sdram_controller = minicon.Minicon(
phy.settings, geom_settings, timing_settings)
self._native_sdram_ifs = []

if sdram_controller_type == "lasmicon":
bridge_if = self.get_native_sdram_if()
if self.l2_size:
lasmim = self.sdram.crossbar.get_master()
l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, wishbone.Interface(lasmim.dw))
l2_cache = wishbone.Cache(self.l2_size//4,
self._cpulevel_sdram_if_arbitrated, bridge_if)
# XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
# Remove this workaround when fixed by Xilinx.
@@ -88,10 +97,20 @@ def register_sdram(self, phy, sdram_controller_type, geom_settings, timing_setti
self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else:
self.submodules.l2_cache = l2_cache
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_cache.slave, lasmim)
elif sdram_controller_type == "minicon":
else:
self.submodules.converter = wishbone.Converter(
self._cpulevel_sdram_if_arbitrated, bridge_if)
elif sdram_controller_type == "lasmicon":
self.submodules.sdram_controller = lasmicon.LASMIcon(
phy.settings, geom_settings, timing_settings)
self.submodules.lasmi_crossbar = lasmi_bus.LASMIxbar(
[self.sdram_controller.lasmic],
self.sdram_controller.nrowbits)

if self.l2_size:
l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, self.sdram.controller.bus)
l2_cache = wishbone.Cache(self.l2_size//4,
self._cpulevel_sdram_if_arbitrated,
wishbone.Interface(bridge_if.dw))
# XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
# Remove this workaround when fixed by Xilinx.
@@ -101,21 +120,43 @@ def register_sdram(self, phy, sdram_controller_type, geom_settings, timing_setti
self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else:
self.submodules.l2_cache = l2_cache
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(
self.l2_cache.slave, bridge_if)
else:
self.submodules.converter = wishbone.Converter(self._wb_sdram, self.sdram.controller.bus)
raise NotImplementedError
else:
raise ValueError
raise ValueError("Incorrect SDRAM controller type specified")
self.comb += self.sdram_controller.dfi.connect(self.dfii.slave)

def do_finalize(self):
if not self.integrated_main_ram_size:
if not self._sdram_phy:
raise FinalizeError("Need to call SDRAMSoC.register_sdram()")
if not self._sdram_phy:
raise FinalizeError("Need to call SDRAMSoC.register_sdram()")

# arbitrate CPU-level interfaces
self.submodules.sdram_cpulevel_arbiter = wishbone.Arbiter(
self._cpulevel_sdram_ifs, self._cpulevel_sdram_if_arbitrated)

# arbitrate native interfaces
# with LASMI, the crossbar is integrated in the controller, we do not
# do anything here.
if hasattr(self, "_native_sdram_ifs"):
self.submodules.sdram_native_arbiter = wishbone.Arbiter(
self._native_sdram_ifs, self.sdram_controller.bus)

# arbitrate wishbone interfaces to the DRAM
self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs,
self._wb_sdram)
SoCCore.do_finalize(self)


soc_sdram_args = soc_core_args
soc_sdram_argdict = soc_core_argdict
def soc_sdram_args(parser):
parser.add_argument("--cpu-type", default=None,
help="select CPU: lm32, or1k")
parser.add_argument("--integrated-rom-size", default=None, type=int,
help="size/enable the integrated (BIOS) ROM")


def soc_sdram_argdict(args):
r = dict()
for a in "cpu_type", "integrated_rom_size":
arg = getattr(args, a)
if arg is not None:
r[a] = arg
return r
2 changes: 1 addition & 1 deletion misoc/interconnect/wishbone.py
Original file line number Diff line number Diff line change
@@ -462,7 +462,7 @@ def __init__(self, cachesize, master, slave):
self.master = master
self.slave = slave

###
# # #

dw_from = len(master.dat_r)
dw_to = len(slave.dat_r)
6 changes: 3 additions & 3 deletions misoc/software/bios/main.c
Original file line number Diff line number Diff line change
@@ -320,7 +320,7 @@ static void help(void)
puts("romboot - boot from embedded rom");
#endif
puts("revision - display revision");
#ifdef CSR_SDRAM_BASE
#ifdef CSR_DFII_BASE
puts("memtest - run a memory test");
#endif
}
@@ -375,7 +375,7 @@ static void do_command(char *c)
else if(strcmp(token, "wcsr") == 0) wcsr(get_token(&c), get_token(&c));
#endif

#ifdef CSR_SDRAM_BASE
#ifdef CSR_DFII_BASE
else if(strcmp(token, "sdrrow") == 0) sdrrow(get_token(&c));
else if(strcmp(token, "sdrsw") == 0) sdrsw();
else if(strcmp(token, "sdrhw") == 0) sdrhw();
@@ -529,7 +529,7 @@ int main(int i, char **c)
#ifdef CSR_ETHMAC_BASE
eth_init();
#endif
#ifdef CSR_SDRAM_BASE
#ifdef CSR_DFII_BASE
sdr_ok = sdrinit();
#else
sdr_ok = 1;
72 changes: 36 additions & 36 deletions misoc/software/bios/sdram.c
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
#include <generated/csr.h>
#ifdef CSR_SDRAM_BASE
#ifdef CSR_DFII_BASE

#include <stdio.h>
#include <stdlib.h>
@@ -27,13 +27,13 @@ static void cdelay(int i)

void sdrsw(void)
{
sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
printf("SDRAM now under software control\n");
}

void sdrhw(void)
{
sdram_dfii_control_write(DFII_CONTROL_SEL);
dfii_control_write(DFII_CONTROL_SEL);
printf("SDRAM now under hardware control\n");
}

@@ -43,8 +43,8 @@ void sdrrow(char *_row)
unsigned int row;

if(*_row == 0) {
sdram_dfii_pi0_address_write(0x0000);
sdram_dfii_pi0_baddress_write(0);
dfii_pi0_address_write(0x0000);
dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(15);
printf("Precharged\n");
@@ -54,8 +54,8 @@ void sdrrow(char *_row)
printf("incorrect row\n");
return;
}
sdram_dfii_pi0_address_write(row);
sdram_dfii_pi0_baddress_write(0);
dfii_pi0_address_write(row);
dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CS);
cdelay(15);
printf("Activated row %d\n", row);
@@ -77,7 +77,7 @@ void sdrrdbuf(int dq)

for(p=0;p<DFII_NPHASES;p++)
for(i=first_byte;i<DFII_PIX_DATA_SIZE;i+=step)
printf("%02x", MMPTR(sdram_dfii_pix_rddata_addr[p]+4*i));
printf("%02x", MMPTR(dfii_pix_rddata_addr[p]+4*i));
printf("\n");
}

@@ -106,8 +106,8 @@ void sdrrd(char *startaddr, char *dq)
}
}

sdram_dfii_pird_address_write(addr);
sdram_dfii_pird_baddress_write(0);
dfii_pird_address_write(addr);
dfii_pird_baddress_write(0);
command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
cdelay(15);
sdrrdbuf(_dq);
@@ -135,13 +135,13 @@ void sdrrderr(char *count)
for(i=0;i<DFII_NPHASES*DFII_PIX_DATA_SIZE;i++)
errs[i] = 0;
for(addr=0;addr<16;addr++) {
sdram_dfii_pird_address_write(addr*8);
sdram_dfii_pird_baddress_write(0);
dfii_pird_address_write(addr*8);
dfii_pird_baddress_write(0);
command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
cdelay(15);
for(p=0;p<DFII_NPHASES;p++)
for(i=0;i<DFII_PIX_DATA_SIZE;i++)
prev_data[p*DFII_PIX_DATA_SIZE+i] = MMPTR(sdram_dfii_pix_rddata_addr[p]+4*i);
prev_data[p*DFII_PIX_DATA_SIZE+i] = MMPTR(dfii_pix_rddata_addr[p]+4*i);

for(j=0;j<_count;j++) {
command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
@@ -150,7 +150,7 @@ void sdrrderr(char *count)
for(i=0;i<DFII_PIX_DATA_SIZE;i++) {
unsigned char new_data;

new_data = MMPTR(sdram_dfii_pix_rddata_addr[p]+4*i);
new_data = MMPTR(dfii_pix_rddata_addr[p]+4*i);
errs[p*DFII_PIX_DATA_SIZE+i] |= prev_data[p*DFII_PIX_DATA_SIZE+i] ^ new_data;
prev_data[p*DFII_PIX_DATA_SIZE+i] = new_data;
}
@@ -185,27 +185,27 @@ void sdrwr(char *startaddr)

for(p=0;p<DFII_NPHASES;p++)
for(i=0;i<DFII_PIX_DATA_SIZE;i++)
MMPTR(sdram_dfii_pix_wrdata_addr[p]+4*i) = 0x10*p + i;
MMPTR(dfii_pix_wrdata_addr[p]+4*i) = 0x10*p + i;

sdram_dfii_piwr_address_write(addr);
sdram_dfii_piwr_baddress_write(0);
dfii_piwr_address_write(addr);
dfii_piwr_baddress_write(0);
command_pwr(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
}

#ifdef CSR_DDRPHY_BASE

void sdrwlon(void)
{
sdram_dfii_pi0_address_write(DDR3_MR1 | (1 << 7));
sdram_dfii_pi0_baddress_write(1);
dfii_pi0_address_write(DDR3_MR1 | (1 << 7));
dfii_pi0_baddress_write(1);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
ddrphy_wlevel_en_write(1);
}

void sdrwloff(void)
{
sdram_dfii_pi0_address_write(DDR3_MR1);
sdram_dfii_pi0_baddress_write(1);
dfii_pi0_address_write(DDR3_MR1);
dfii_pi0_baddress_write(1);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
ddrphy_wlevel_en_write(0);
}
@@ -224,7 +224,7 @@ static int write_level(int *delay, int *high_skew)
sdrwlon();
cdelay(100);
for(i=0;i<DFII_PIX_DATA_SIZE/2;i++) {
dq_address = sdram_dfii_pix_rddata_addr[0]+4*(DFII_PIX_DATA_SIZE/2-1-i);
dq_address = dfii_pix_rddata_addr[0]+4*(DFII_PIX_DATA_SIZE/2-1-i);
ddrphy_dly_sel_write(1 << i);
ddrphy_wdly_dq_rst_write(1);
ddrphy_wdly_dqs_rst_write(1);
@@ -326,22 +326,22 @@ static void read_delays(void)
}

/* Activate */
sdram_dfii_pi0_address_write(0);
sdram_dfii_pi0_baddress_write(0);
dfii_pi0_address_write(0);
dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CS);
cdelay(15);

/* Write test pattern */
for(p=0;p<DFII_NPHASES;p++)
for(i=0;i<DFII_PIX_DATA_SIZE;i++)
MMPTR(sdram_dfii_pix_wrdata_addr[p]+4*i) = prs[DFII_PIX_DATA_SIZE*p+i];
sdram_dfii_piwr_address_write(0);
sdram_dfii_piwr_baddress_write(0);
MMPTR(dfii_pix_wrdata_addr[p]+4*i) = prs[DFII_PIX_DATA_SIZE*p+i];
dfii_piwr_address_write(0);
dfii_piwr_baddress_write(0);
command_pwr(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);

/* Calibrate each DQ in turn */
sdram_dfii_pird_address_write(0);
sdram_dfii_pird_baddress_write(0);
dfii_pird_address_write(0);
dfii_pird_baddress_write(0);
for(i=0;i<DFII_PIX_DATA_SIZE/2;i++) {
ddrphy_dly_sel_write(1 << (DFII_PIX_DATA_SIZE/2-i-1));
delay = 0;
@@ -353,9 +353,9 @@ static void read_delays(void)
cdelay(15);
working = 1;
for(p=0;p<DFII_NPHASES;p++) {
if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*i) != prs[DFII_PIX_DATA_SIZE*p+i])
if(MMPTR(dfii_pix_rddata_addr[p]+4*i) != prs[DFII_PIX_DATA_SIZE*p+i])
working = 0;
if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(i+DFII_PIX_DATA_SIZE/2)) != prs[DFII_PIX_DATA_SIZE*p+i+DFII_PIX_DATA_SIZE/2])
if(MMPTR(dfii_pix_rddata_addr[p]+4*(i+DFII_PIX_DATA_SIZE/2)) != prs[DFII_PIX_DATA_SIZE*p+i+DFII_PIX_DATA_SIZE/2])
working = 0;
}
if(working)
@@ -377,9 +377,9 @@ static void read_delays(void)
cdelay(15);
working = 1;
for(p=0;p<DFII_NPHASES;p++) {
if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*i) != prs[DFII_PIX_DATA_SIZE*p+i])
if(MMPTR(dfii_pix_rddata_addr[p]+4*i) != prs[DFII_PIX_DATA_SIZE*p+i])
working = 0;
if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(i+DFII_PIX_DATA_SIZE/2)) != prs[DFII_PIX_DATA_SIZE*p+i+DFII_PIX_DATA_SIZE/2])
if(MMPTR(dfii_pix_rddata_addr[p]+4*(i+DFII_PIX_DATA_SIZE/2)) != prs[DFII_PIX_DATA_SIZE*p+i+DFII_PIX_DATA_SIZE/2])
working = 0;
}
if(!working)
@@ -400,8 +400,8 @@ static void read_delays(void)
}

/* Precharge */
sdram_dfii_pi0_address_write(0);
sdram_dfii_pi0_baddress_write(0);
dfii_pi0_address_write(0);
dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(15);

@@ -537,7 +537,7 @@ int sdrinit(void)
if(!sdrlevel())
return 0;
#endif
sdram_dfii_control_write(DFII_CONTROL_SEL);
dfii_control_write(DFII_CONTROL_SEL);
if(!memtest())
return 0;

2 changes: 1 addition & 1 deletion misoc/software/unwinder
Submodule unwinder updated from 543f84 to 8b1196
9 changes: 4 additions & 5 deletions misoc/targets/de0nano.py
Original file line number Diff line number Diff line change
@@ -94,11 +94,10 @@ def __init__(self, **kwargs):

self.submodules.crg = _CRG(platform)

if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = IS42S16160(self.clk_freq)
self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = IS42S16160(self.clk_freq)
self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)

def main():
parser = argparse.ArgumentParser(description="MiSoC port to the Altera DE0 Nano")
9 changes: 4 additions & 5 deletions misoc/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -91,11 +91,10 @@ def __init__(self, toolchain="ise", sdram_controller_type="minicon", **kwargs):

self.submodules.crg = _CRG(platform)

if not self.integrated_main_ram_size:
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq)
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings, sdram_module.timing_settings)
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq)
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings, sdram_module.timing_settings)

if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash")
25 changes: 12 additions & 13 deletions misoc/targets/mimasv2.py
Original file line number Diff line number Diff line change
@@ -107,19 +107,18 @@ def __init__(self, clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):

self.submodules.crg = _CRG(platform, clk_freq)

if not self.integrated_main_ram_size:
sdram_module = MT46H32M16(self.clk_freq)
self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram(self.ddrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)
sdram_module = MT46H32M16(self.clk_freq)
self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram(self.ddrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)


def main():
9 changes: 4 additions & 5 deletions misoc/targets/minispartan6.py
Original file line number Diff line number Diff line change
@@ -74,11 +74,10 @@ def __init__(self, **kwargs):

self.submodules.crg = _CRG(platform, clk_freq)

if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = AS4C16M16(clk_freq)
self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = AS4C16M16(clk_freq)
self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)


def main():
27 changes: 13 additions & 14 deletions misoc/targets/mlabs_video.py
Original file line number Diff line number Diff line change
@@ -88,19 +88,18 @@ def __init__(self, platform_name="mixxeo", **kwargs):

self.submodules.crg = _MXCRG(_MXClockPads(platform), self.clk_freq)

if not self.integrated_main_ram_size:
sdram_module = MT46V32M16(self.clk_freq)
self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=0,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.register_sdram(self.ddrphy, "lasmicon",
sdram_module.geom_settings, sdram_module.timing_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
]
sdram_module = MT46V32M16(self.clk_freq)
self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=0,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.register_sdram(self.ddrphy, "lasmicon",
sdram_module.geom_settings, sdram_module.timing_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
]

if not self.integrated_rom_size:
clk_period_ns = 1000000000/self.clk_freq
@@ -187,7 +186,7 @@ def __init__(self, *args, **kwargs):
MiniSoC.__init__(self, *args, **kwargs)
pads_vga, pads_dvi = get_vga_dvi(platform)
self.submodules.fb = framebuffer.Framebuffer(pads_vga, pads_dvi,
self.sdram.crossbar.get_master())
self.get_native_sdram_if())
add_vga_tig(platform, self.fb)


9 changes: 4 additions & 5 deletions misoc/targets/papilio_pro.py
Original file line number Diff line number Diff line change
@@ -80,11 +80,10 @@ def __init__(self, **kwargs):

self.submodules.crg = _CRG(platform, clk_freq)

if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC4M16(clk_freq)
self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC4M16(clk_freq)
self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)

if not self.integrated_rom_size:
self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash2x"),
25 changes: 12 additions & 13 deletions misoc/targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -108,19 +108,18 @@ def __init__(self, clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):

self.submodules.crg = _CRG(platform, clk_freq)

if not self.integrated_main_ram_size:
sdram_module = MT46H32M16(self.clk_freq)
self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram(self.ddrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)
sdram_module = MT46H32M16(self.clk_freq)
self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram(self.ddrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)

if not self.integrated_rom_size:
self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash4x"),

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