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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: aac34f011f37
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Nov 30, 2014

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    8ae3a00 View commit details
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    aac34f0 View commit details
Showing with 38 additions and 34 deletions.
  1. +2 −2 make.py
  2. +12 −5 misoclib/gensoc/__init__.py
  3. +24 −27 misoclib/gensoc/cpuif.py
4 changes: 2 additions & 2 deletions make.py
Original file line number Diff line number Diff line change
@@ -152,15 +152,15 @@ def _get_args():
flash_boot_address = None
mem_header = cpuif.get_mem_header(soc.cpu_memory_regions, flash_boot_address)
write_to_file("software/include/generated/mem.h", boilerplate + mem_header)
csr_header = cpuif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
csr_header = cpuif.get_csr_header(soc.cpu_csr_regions, soc.interrupt_map)
write_to_file("software/include/generated/csr.h", boilerplate + csr_header)
for sdram_phy in ["sdrphy", "ddrphy"]:
if hasattr(soc, sdram_phy):
sdram_phy_header = initsequence.get_sdram_phy_header(getattr(soc, sdram_phy))
write_to_file("software/include/generated/sdram_phy.h", boilerplate + sdram_phy_header)

if actions["build-csr-csv"]:
csr_csv = cpuif.get_csr_csv(soc.csr_base, soc.csrbankarray)
csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
write_to_file(args.csr_csv, csr_csv)

if actions["build-bios"]:
17 changes: 12 additions & 5 deletions misoclib/gensoc/__init__.py
Original file line number Diff line number Diff line change
@@ -14,7 +14,6 @@
from misoclib.sdram.minicon import Minicon

class GenSoC(Module):
csr_base = 0xe0000000
csr_map = {
"crg": 0, # user
"uart": 1, # provided by default
@@ -41,6 +40,7 @@ def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_siz
self.l2_size = l2_size
self.cpu_type = cpu_type
self.cpu_memory_regions = []
self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
self._rom_registered = False

# Wishbone
@@ -59,7 +59,7 @@ def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_siz
self._wb_masters = [self.cpu.ibus, self.cpu.dbus]
self._wb_slaves = [
(lambda a: a[26:29] == 1, self.sram.bus),
(lambda a: a[27:29] == 3, self.wishbone2csr.wishbone)
(lambda a: a[26:29] == 6, self.wishbone2csr.wishbone)
]
self.add_cpu_memory_region("sram", 0x10000000, sram_size)

@@ -103,6 +103,9 @@ def add_wb_slave(self, address_decoder, interface):
def add_cpu_memory_region(self, name, origin, length):
self.cpu_memory_regions.append((name, origin, length))

def add_cpu_csr_region(self, name, origin, busword, obj):
self.cpu_csr_regions.append((name, origin, busword, obj))

def do_finalize(self):
if not self._rom_registered:
raise FinalizeError("Need to call GenSoC.register_rom()")
@@ -115,6 +118,10 @@ def do_finalize(self):
self.submodules.csrbankarray = csrgen.BankArray(self,
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)

# Interrupts
for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
@@ -173,7 +180,7 @@ def register_sdram_phy(self, phy_dfi, phy_settings, sdram_geom, sdram_timing):

# Wishbone bridge: map SDRAM at 0x40000000 (shadow @0xc0000000)
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master())
self.add_wb_slave(lambda a: a[27:29] == 2, self.wishbone2lasmi.wishbone)
self.add_wb_slave(lambda a: a[26:29] == 4, self.wishbone2lasmi.wishbone)
self.add_cpu_memory_region("sdram", 0x40000000,
2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8)
elif self.ramcon_type == "minicon":
@@ -182,11 +189,11 @@ def register_sdram_phy(self, phy_dfi, phy_settings, sdram_geom, sdram_timing):
sdram_width = flen(sdramcon.bus.dat_r)

if (sdram_width == 32):
self.add_wb_slave(lambda a: a[27:29] == 2, sdramcon.bus)
self.add_wb_slave(lambda a: a[26:29] == 4, sdramcon.bus)
elif (sdram_width < 32):
self.submodules.dc = dc = wishbone.DownConverter(32, sdram_width)
self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, sdramcon.bus)
self.add_wb_slave(lambda a: a[27:29] == 2, dc.wishbone_i)
self.add_wb_slave(lambda a: a[26:29] == 4, dc.wishbone_i)
else:
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))

51 changes: 24 additions & 27 deletions misoclib/gensoc/cpuif.py
Original file line number Diff line number Diff line change
@@ -68,37 +68,34 @@ def _get_rw_functions(reg_name, reg_base, nwords, busword, read_only):
r += "}\n"
return r

def get_csr_header(csr_base, bank_array, interrupt_map):
def get_csr_header(regions, interrupt_map):
r = "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n#include <hw/common.h>\n"
for name, csrs, mapaddr, rmap in bank_array.banks:
r += "\n/* "+name+" */\n"
reg_base = csr_base + 0x800*mapaddr
r += "#define "+name.upper()+"_BASE "+hex(reg_base)+"\n"
busword = flen(rmap.bus.dat_w)
for csr in csrs:
nr = (csr.size + busword - 1)//busword
r += _get_rw_functions(name + "_" + csr.name, reg_base, nr, busword, isinstance(csr, CSRStatus))
reg_base += 4*nr
try:
interrupt_nr = interrupt_map[name]
except KeyError:
pass
for name, origin, busword, obj in regions:
if isinstance(obj, Memory):
fullname = name + "_" + memory.name_override
r += "#define "+fullname.upper()+"_BASE "+hex(origin)+"\n"
else:
r += "#define "+name.upper()+"_INTERRUPT "+str(interrupt_nr)+"\n"
for name, memory, mapaddr, mmap in bank_array.srams:
mem_base = csr_base + 0x800*mapaddr
fullname = name + "_" + memory.name_override
r += "#define "+fullname.upper()+"_BASE "+hex(mem_base)+"\n"
r += "\n/* "+name+" */\n"
r += "#define "+name.upper()+"_BASE "+hex(origin)+"\n"
for csr in obj:
nr = (csr.size + busword - 1)//busword
r += _get_rw_functions(name + "_" + csr.name, origin, nr, busword, isinstance(csr, CSRStatus))
origin += 4*nr
try:
interrupt_nr = interrupt_map[name]
except KeyError:
pass
else:
r += "#define "+name.upper()+"_INTERRUPT "+str(interrupt_nr)+"\n"
r += "\n#endif\n"
return r

def get_csr_csv(csr_base, bank_array):
def get_csr_csv(regions):
r = ""
for name, csrs, mapaddr, rmap in bank_array.banks:
reg_base = csr_base + 0x800*mapaddr
busword = flen(rmap.bus.dat_w)
for csr in csrs:
nr = (csr.size + busword - 1)//busword
r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, reg_base, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
reg_base += 4*nr
for name, origin, busword, obj in regions:
if not isinstance(obj, Memory):
for csr in obj:
nr = (csr.size + busword - 1)//busword
r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
origin += 4*nr
return r