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Commit b4e041e

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author
Sebastien Bourdeauducq
committedFeb 20, 2012
s6ddrphy: write path OK in simulation
·
0.120.1
1 parent ce51653 commit b4e041e

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7 files changed

+209
-62
lines changed

7 files changed

+209
-62
lines changed
 

‎milkymist/m1crg/__init__.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ def __init__(self, infreq, outfreq1x):
1414
"ac97_rst_n",
1515
"videoin_rst_n",
1616
"flash_rst_n",
17-
"clk2x_90",
17+
"clk2x_270",
1818
"clk4x_wr",
1919
"clk4x_wr_strb",
2020
"clk4x_rd",

‎milkymist/s6ddrphy/__init__.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ def __init__(self, a, ba, d):
88
inouts = []
99

1010
for name in [
11-
"clk2x_90",
11+
"clk2x_270",
1212
"clk4x_wr",
1313
"clk4x_wr_strb",
1414
"clk4x_rd",

‎tb/s6ddrphy/Makefile

+23
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
SOURCES=tb_s6ddrphy.v ../../verilog/s6ddrphy/s6ddrphy.v \
2+
$(XILINX)/verilog/src/unisims/ODDR2.v \
3+
$(XILINX)/verilog/src/unisims/OSERDES2.v \
4+
$(XILINX)/verilog/src/unisims/ISERDES2.v \
5+
$(XILINX)/verilog/src/unisims/IOBUF.v \
6+
$(XILINX)/verilog/src/unisims/OBUFT.v \
7+
$(XILINX)/verilog/src/unisims/BUFPLL.v
8+
9+
all: tb_s6ddrphy
10+
11+
isim: tb_s6ddrphy
12+
./tb_s6ddrphy
13+
14+
cversim: $(SOURCES)
15+
cver $(SOURCES)
16+
17+
clean:
18+
rm -f tb_s6ddrphy verilog.log s6ddrphy.vcd
19+
20+
tb_s6ddrphy: $(SOURCES)
21+
iverilog -o tb_s6ddrphy $(SOURCES)
22+
23+
.PHONY: clean sim cversim

‎tb/s6ddrphy/tb_s6ddrphy.v

+125
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,125 @@
1+
`timescale 1ns / 1ps
2+
3+
module tb_s6ddrphy();
4+
5+
reg sys_clk = 1'b0;
6+
reg clk2x_270 = 1'b0;
7+
reg clk4x_wr = 1'b0;
8+
wire clk4x_wr_strb;
9+
wire clk4x_rd = clk4x_wr;
10+
wire clk4x_rd_strb = clk4x_wr_strb;
11+
12+
initial begin
13+
while(1) begin
14+
sys_clk <= 1'b1;
15+
#6;
16+
sys_clk <= 1'b0;
17+
#6;
18+
end
19+
end
20+
21+
initial begin
22+
#4.5;
23+
while(1) begin
24+
clk2x_270 <= 1'b1;
25+
#3;
26+
clk2x_270 <= 1'b0;
27+
#3;
28+
end
29+
end
30+
31+
initial begin
32+
while(1) begin
33+
clk4x_wr <= 1'b1;
34+
#1.5;
35+
clk4x_wr <= 1'b0;
36+
#1.5;
37+
end
38+
end
39+
40+
BUFPLL #(
41+
.DIVIDE(4)
42+
) bufpll (
43+
.PLLIN(clk4x_wr),
44+
.GCLK(sys_clk),
45+
.LOCKED(1'b1),
46+
.IOCLK(),
47+
.LOCK(),
48+
.SERDESSTROBE(clk4x_wr_strb)
49+
);
50+
51+
reg [12:0] dfi_address_p0 = 0;
52+
reg [12:0] dfi_address_p1 = 0;
53+
54+
reg dfi_wrdata_en_p0 = 0;
55+
reg [7:0] dfi_wrdata_mask_p0 = 0;
56+
reg [63:0] dfi_wrdata_p0 = 0;
57+
reg dfi_wrdata_en_p1 = 0;
58+
reg [7:0] dfi_wrdata_mask_p1 = 0;
59+
reg [63:0] dfi_wrdata_p1 = 0;
60+
61+
s6ddrphy #(
62+
.NUM_AD(13),
63+
.NUM_BA(2),
64+
.NUM_D(64)
65+
) dut (
66+
.sys_clk(sys_clk),
67+
.clk2x_270(clk2x_270),
68+
.clk4x_wr(clk4x_wr),
69+
.clk4x_wr_strb(clk4x_wr_strb),
70+
.clk4x_rd(clk4x_rd),
71+
.clk4x_rd_strb(clk4x_rd_strb),
72+
73+
.sd_clk_out_p(),
74+
.sd_clk_out_n(),
75+
76+
.dfi_address_p0(dfi_address_p0),
77+
.dfi_address_p1(dfi_address_p1),
78+
.sd_a(),
79+
80+
.dfi_wrdata_en_p0(dfi_wrdata_en_p0),
81+
.dfi_wrdata_mask_p0(dfi_wrdata_mask_p0),
82+
.dfi_wrdata_p0(dfi_wrdata_p0),
83+
.dfi_wrdata_en_p1(dfi_wrdata_en_p1),
84+
.dfi_wrdata_mask_p1(dfi_wrdata_mask_p1),
85+
.dfi_wrdata_p1(dfi_wrdata_p1),
86+
.sd_dq(),
87+
.sd_dm(),
88+
.sd_dqs()
89+
);
90+
91+
initial begin
92+
$dumpfile("s6ddrphy.vcd");
93+
$dumpvars(3, dut);
94+
#13;
95+
96+
/*dfi_address_p0 <= 13'h1aba;
97+
dfi_address_p1 <= 13'h1234;
98+
#12;
99+
dfi_address_p0 <= 0;
100+
dfi_address_p1 <= 0;
101+
#60;*/
102+
103+
dfi_address_p0 <= 13'h0dea;
104+
dfi_address_p1 <= 13'h0dbe;
105+
dfi_wrdata_p0 <= 64'hcafebabeabadface;
106+
dfi_wrdata_p1 <= 64'h0123456789abcdef;
107+
dfi_wrdata_en_p0 <= 1'b1;
108+
dfi_wrdata_en_p1 <= 1'b1;
109+
#12;
110+
dfi_address_p0 <= 0;
111+
dfi_address_p1 <= 0;
112+
dfi_wrdata_p0 <= 64'd0;
113+
dfi_wrdata_p1 <= 64'd0;
114+
dfi_wrdata_en_p0 <= 1'b0;
115+
dfi_wrdata_en_p1 <= 1'b0;
116+
#60;
117+
$finish;
118+
end
119+
120+
endmodule
121+
122+
module glbl();
123+
wire GSR = 1'b0;
124+
wire GTS = 1'b0;
125+
endmodule

‎top.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@
1818

1919
def ddrphy_clocking(crg, phy):
2020
names = [
21-
"clk2x_90",
21+
"clk2x_270",
2222
"clk4x_wr",
2323
"clk4x_wr_strb",
2424
"clk4x_rd",

‎verilog/m1crg/m1crg.v

+3-3
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ module m1crg #(
3333
output flash_rst_n,
3434

3535
/* DDR PHY clocks */
36-
output clk2x_90,
36+
output clk2x_270,
3737
output clk4x_wr,
3838
output clk4x_wr_strb,
3939
output clk4x_rd,
@@ -122,7 +122,7 @@ PLL_ADV #(
122122
.CLKOUT1_PHASE(0),
123123
.CLKOUT2_DIVIDE(2*f_div),
124124
.CLKOUT2_DUTY_CYCLE(0.5),
125-
.CLKOUT2_PHASE(90.0),
125+
.CLKOUT2_PHASE(270.0),
126126
.CLKOUT3_DIVIDE(4*f_div),
127127
.CLKOUT3_DUTY_CYCLE(0.5),
128128
.CLKOUT3_PHASE(0.0),
@@ -192,7 +192,7 @@ BUFPLL #(
192192

193193
BUFG bufg_x2_2(
194194
.I(pllout2),
195-
.O(clk2x_90)
195+
.O(clk2x_270)
196196
);
197197

198198
BUFG bufg_x1(

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