s6ddrphy: write path OK in simulation

m-labs · Feb 20, 2012 · b4e041e · b4e041e
1 parent ce51653
commit b4e041e
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Showing 7 changed files with 209 additions and 62 deletions.
diff --git a/milkymist/m1crg/__init__.py b/milkymist/m1crg/__init__.py
@@ -14,7 +14,7 @@ def __init__(self, infreq, outfreq1x):
 			"ac97_rst_n",
 			"videoin_rst_n",
 			"flash_rst_n",
-			"clk2x_90",
+			"clk2x_270",
 			"clk4x_wr",
 			"clk4x_wr_strb",
 			"clk4x_rd",

diff --git a/milkymist/s6ddrphy/__init__.py b/milkymist/s6ddrphy/__init__.py
@@ -8,7 +8,7 @@ def __init__(self, a, ba, d):
 		inouts = []
 
 		for name in [
-			"clk2x_90",
+			"clk2x_270",
 			"clk4x_wr",
 			"clk4x_wr_strb",
 			"clk4x_rd",

diff --git a/tb/s6ddrphy/Makefile b/tb/s6ddrphy/Makefile
@@ -0,0 +1,23 @@
+SOURCES=tb_s6ddrphy.v ../../verilog/s6ddrphy/s6ddrphy.v \
+	$(XILINX)/verilog/src/unisims/ODDR2.v \
+	$(XILINX)/verilog/src/unisims/OSERDES2.v \
+	$(XILINX)/verilog/src/unisims/ISERDES2.v \
+	$(XILINX)/verilog/src/unisims/IOBUF.v \
+	$(XILINX)/verilog/src/unisims/OBUFT.v \
+	$(XILINX)/verilog/src/unisims/BUFPLL.v
+
+all: tb_s6ddrphy
+
+isim: tb_s6ddrphy
+	./tb_s6ddrphy
+
+cversim: $(SOURCES)
+	cver $(SOURCES)
+
+clean:
+	rm -f tb_s6ddrphy verilog.log s6ddrphy.vcd
+
+tb_s6ddrphy: $(SOURCES)
+	iverilog -o tb_s6ddrphy $(SOURCES)
+
+.PHONY: clean sim cversim
diff --git a/tb/s6ddrphy/tb_s6ddrphy.v b/tb/s6ddrphy/tb_s6ddrphy.v
@@ -0,0 +1,125 @@
+`timescale 1ns / 1ps
+
+module tb_s6ddrphy();
+
+reg sys_clk = 1'b0;
+reg clk2x_270 = 1'b0;
+reg clk4x_wr = 1'b0;
+wire clk4x_wr_strb;
+wire clk4x_rd = clk4x_wr;
+wire clk4x_rd_strb = clk4x_wr_strb;
+
+initial begin
+	while(1) begin
+		sys_clk <= 1'b1;
+		#6;
+		sys_clk <= 1'b0;
+		#6;
+	end
+end
+
+initial begin
+	#4.5;
+	while(1) begin
+		clk2x_270 <= 1'b1;
+		#3;
+		clk2x_270 <= 1'b0;
+		#3;
+	end
+end
+
+initial begin
+	while(1) begin
+		clk4x_wr <= 1'b1;
+		#1.5;
+		clk4x_wr <= 1'b0;
+		#1.5;
+	end
+end
+
+BUFPLL #(
+	.DIVIDE(4)
+) bufpll (
+	.PLLIN(clk4x_wr),
+	.GCLK(sys_clk),
+	.LOCKED(1'b1),
+	.IOCLK(),
+	.LOCK(),
+	.SERDESSTROBE(clk4x_wr_strb)
+);
+
+reg [12:0] dfi_address_p0 = 0;
+reg [12:0] dfi_address_p1 = 0;
+
+reg dfi_wrdata_en_p0 = 0;
+reg [7:0] dfi_wrdata_mask_p0 = 0;
+reg [63:0] dfi_wrdata_p0 = 0;
+reg dfi_wrdata_en_p1 = 0;
+reg [7:0] dfi_wrdata_mask_p1 = 0;
+reg [63:0] dfi_wrdata_p1 = 0;
+
+s6ddrphy #(
+	.NUM_AD(13),
+	.NUM_BA(2),
+	.NUM_D(64)
+) dut (
+	.sys_clk(sys_clk),
+	.clk2x_270(clk2x_270),
+	.clk4x_wr(clk4x_wr),
+	.clk4x_wr_strb(clk4x_wr_strb),
+	.clk4x_rd(clk4x_rd),
+	.clk4x_rd_strb(clk4x_rd_strb),
+
+	.sd_clk_out_p(),
+	.sd_clk_out_n(),
+
+	.dfi_address_p0(dfi_address_p0),
+	.dfi_address_p1(dfi_address_p1),
+	.sd_a(),
+
+	.dfi_wrdata_en_p0(dfi_wrdata_en_p0),
+	.dfi_wrdata_mask_p0(dfi_wrdata_mask_p0),
+	.dfi_wrdata_p0(dfi_wrdata_p0),
+	.dfi_wrdata_en_p1(dfi_wrdata_en_p1),
+	.dfi_wrdata_mask_p1(dfi_wrdata_mask_p1),
+	.dfi_wrdata_p1(dfi_wrdata_p1),
+	.sd_dq(),
+	.sd_dm(),
+	.sd_dqs()
+);
+
+initial begin
+	$dumpfile("s6ddrphy.vcd");
+	$dumpvars(3, dut);
+	#13;
+
+	/*dfi_address_p0 <= 13'h1aba;
+	dfi_address_p1 <= 13'h1234;
+	#12;
+	dfi_address_p0 <= 0;
+	dfi_address_p1 <= 0;
+	#60;*/
+
+	dfi_address_p0 <= 13'h0dea;
+	dfi_address_p1 <= 13'h0dbe;
+	dfi_wrdata_p0 <= 64'hcafebabeabadface;
+	dfi_wrdata_p1 <= 64'h0123456789abcdef;
+	dfi_wrdata_en_p0 <= 1'b1;
+	dfi_wrdata_en_p1 <= 1'b1;
+	#12;
+	dfi_address_p0 <= 0;
+	dfi_address_p1 <= 0;
+	dfi_wrdata_p0 <= 64'd0;
+	dfi_wrdata_p1 <= 64'd0;
+	dfi_wrdata_en_p0 <= 1'b0;
+	dfi_wrdata_en_p1 <= 1'b0;
+	#60;
+	$finish;
+end
+
+endmodule
+
+module glbl();
+wire GSR = 1'b0;
+wire GTS = 1'b0;
+endmodule
diff --git a/top.py b/top.py
@@ -18,7 +18,7 @@
 
 def ddrphy_clocking(crg, phy):
 	names = [
-		"clk2x_90",
+		"clk2x_270",
 		"clk4x_wr",
 		"clk4x_wr_strb",
 		"clk4x_rd",

diff --git a/verilog/m1crg/m1crg.v b/verilog/m1crg/m1crg.v
@@ -33,7 +33,7 @@ module m1crg #(
 	output flash_rst_n,
 
 	/* DDR PHY clocks */
-	output clk2x_90,
+	output clk2x_270,
 	output clk4x_wr,
 	output clk4x_wr_strb,
 	output clk4x_rd,
@@ -122,7 +122,7 @@ PLL_ADV #(
 	.CLKOUT1_PHASE(0),
 	.CLKOUT2_DIVIDE(2*f_div),
 	.CLKOUT2_DUTY_CYCLE(0.5),
-	.CLKOUT2_PHASE(90.0),
+	.CLKOUT2_PHASE(270.0),
 	.CLKOUT3_DIVIDE(4*f_div),
 	.CLKOUT3_DUTY_CYCLE(0.5),
 	.CLKOUT3_PHASE(0.0),
@@ -192,7 +192,7 @@ BUFPLL #(
 
 BUFG bufg_x2_2(
 	.I(pllout2),
-	.O(clk2x_90)
+	.O(clk2x_270)
 );
 
 BUFG bufg_x1(