edid.py: sample SCL only every 64 clock cycles, to avoid bouncing

Possibly due to SCL rising fairly slowly (in the 0.5-1 us range), bouncing has been observed while crossing the "forbidden" region between Vil(max) and Vih(min). By lowering the sample rate from once per system clock to once every 64 clock cycles, we make sure we sample at most once during the bounce interval and thus never see a false edge. (Although we may see a rising edge one sample time late, which is perfectly harmless.)
m-labs · Apr 12, 2013 · 7a6e564 · 7a6e564
1 parent 950d3a4
commit 7a6e564
Showing 1 changed file with 9 additions and 8 deletions.
diff --git a/milkymist/dvisampler/edid.py b/milkymist/dvisampler/edid.py
@@ -23,24 +23,25 @@ def __init__(self, pads, default=_default_edid):
 
 		###
 
-		scl_i = Signal()
+		scl_raw = Signal()
 		sda_i = Signal()
 		sda_drv = Signal()
 		_sda_drv_reg = Signal()
 		_sda_i_async = Signal()
 		self.sync += _sda_drv_reg.eq(sda_drv)
 		self.specials += [
-			MultiReg(pads.scl, scl_i),
+			MultiReg(pads.scl, scl_raw),
 			Tristate(pads.sda, 0, _sda_drv_reg, _sda_i_async),
 			MultiReg(_sda_i_async, sda_i)
 		]
 
-		# FIXME: understand what is really going on here and get rid of that workaround
-		for x in range(20):
-			new_scl = Signal()
-			self.sync += new_scl.eq(scl_i)
-			scl_i = new_scl
-		#
+		scl_i = Signal()
+		samp_count = Signal(6)
+		samp_carry = Signal()
+		self.sync += [
+			Cat(samp_count, samp_carry).eq(samp_count + 1),
+			If(samp_carry, scl_i.eq(scl_raw))
+		]
 
 		scl_r = Signal()
 		sda_r = Signal()