9
9
from migen .fhdl .module import Module
10
10
from migen .fhdl import verilog
11
11
from migen .genlib .misc import optree
12
- from migen .fhdl import autofragment
13
12
from migen .sim .generic import Simulator
14
13
15
14
# A synthesizable FIR filter.
16
- class FIR :
15
+ class FIR ( Module ) :
17
16
def __init__ (self , coef , wsize = 16 ):
18
17
self .coef = coef
19
18
self .wsize = wsize
20
19
self .i = Signal ((self .wsize , True ))
21
20
self .o = Signal ((self .wsize , True ))
22
21
23
- def get_fragment (self ):
22
+ ###
23
+
24
24
muls = []
25
- sync = []
26
25
src = self .i
27
26
for c in self .coef :
28
27
sreg = Signal ((self .wsize , True ))
29
- sync . append ( sreg .eq (src ) )
28
+ self . sync += sreg .eq (src )
30
29
src = sreg
31
30
c_fp = int (c * 2 ** (self .wsize - 1 ))
32
31
muls .append (c_fp * sreg )
33
32
sum_full = Signal ((2 * self .wsize - 1 , True ))
34
- sync .append (sum_full .eq (optree ("+" , muls )))
35
- comb = [self .o .eq (sum_full [self .wsize - 1 :])]
36
- return Fragment (comb , sync )
33
+ self .sync += sum_full .eq (optree ("+" , muls ))
34
+ self .comb += self .o .eq (sum_full [self .wsize - 1 :])
37
35
38
36
# A test bench for our FIR filter.
39
37
# Generates a sine wave at the input and records the output.
40
38
class TB (Module ):
41
- def __init__ (self , fir , frequency ):
42
- self .fir = fir
39
+ def __init__ (self , coef , frequency ):
40
+ self .submodules . fir = FIR ( coef )
43
41
self .frequency = frequency
44
42
self .inputs = []
45
43
self .outputs = []
@@ -54,16 +52,14 @@ def do_simulation(self, s):
54
52
def main ():
55
53
# Compute filter coefficients with SciPy.
56
54
coef = signal .remez (30 , [0 , 0.1 , 0.2 , 0.4 , 0.45 , 0.5 ], [0 , 1 , 0 ])
57
- fir = FIR (coef )
58
55
59
56
# Simulate for different frequencies and concatenate
60
57
# the results.
61
58
in_signals = []
62
59
out_signals = []
63
60
for frequency in [0.05 , 0.1 , 0.25 ]:
64
- tb = TB (fir , frequency )
65
- fragment = autofragment .from_local ()
66
- sim = Simulator (fragment )
61
+ tb = TB (coef , frequency )
62
+ sim = Simulator (tb )
67
63
sim .run (200 )
68
64
del sim
69
65
in_signals += tb .inputs
@@ -75,7 +71,7 @@ def main():
75
71
plt .show ()
76
72
77
73
# Print the Verilog source for the filter.
78
- print ( verilog . convert ( fir . get_fragment (),
79
- ios = {fir .i , fir .o }))
74
+ fir = FIR ( coef )
75
+ print ( verilog . convert ( fir , ios = {fir .i , fir .o }))
80
76
81
77
main ()
0 commit comments