fhdl/specials/Instance: _printintbool -> verilog_printexpr

m-labs · Feb 24, 2013 · 55ab01f · 55ab01f
1 parent c2d54f4
commit 55ab01f
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
@@ -127,7 +127,7 @@ def emit_verilog(instance, ns, clock_domains):
 				firstp = False
 				r += "\t." + p.name + "("
 				if isinstance(p.value, (int, bool)):
-					r += _printintbool(p.value)[0]
+					r += verilog_printexpr(ns, p.value)[0]
 				elif isinstance(p.value, float):
 					r += str(p.value)
 				elif isinstance(p.value, str):