-
Notifications
You must be signed in to change notification settings - Fork 201
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
doc/manual: add FPGA board info and TTL line assignments
1 parent
35d4f75
commit 8d59f84
Showing
1 changed file
with
26 additions
and
0 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,26 @@ | ||
FPGA board ports | ||
================ | ||
|
||
KC705 | ||
----- | ||
|
||
The main target board for the ARTIQ core device is the KC705 development board from Xilinx. | ||
|
||
Papilio Pro | ||
----------- | ||
|
||
The low-cost Papilio Pro FPGA board can be used with some limitations. | ||
|
||
When plugged to a QC-DAQ LVDS adapter, the AD9858 DDS hardware can be used in addition to a limited number of TTL channels. The TTL lines are mapped to RTIO channels as follows: | ||
|
||
+--------------+----------+----------------+ | ||
| RTIO channel | TTL line | Capability | | ||
+==============+==========+================+ | ||
| 0 | PMT0 | Output + input | | ||
+--------------+----------+----------------+ | ||
| 1 | TTL0 | Output only | | ||
+--------------+----------+----------------+ | ||
| 2 | TTL1 | Output only | | ||
+--------------+----------+----------------+ | ||
| 3 | TTL2 | Output only | | ||
+--------------+----------+----------------+ |