m-labs · Aug 3, 2014 · Aug 3, 2014
Showing with 39 additions and 5 deletions.

+8 −5 README

+31 −0 targets/kc705.py
diff --git a/README b/README
@@ -9,6 +9,7 @@ a high performance and small footprint SoC based on Migen
 [> Features
 -----------
  * LatticeMico32 CPU, modified to include an optional MMU (experimental).
+ * mor1kx (a better OpenRISC implementation) as alternative CPU option.
  * High performance memory controller capable of issuing several SDRAM commands
    per FPGA cycle.
  * Supports SDR, DDR, LPDDR and DDR2.
@@ -27,6 +28,7 @@ MiSoC comes with built-in support for the following boards:
  * Mixxeo, the digital video mixer from M-Labs [XC6SLX45]
  * Milkymist One, the original M-Labs video synthesizer [XC6SLX45]
  * Papilio Pro, a simple and low-cost development board [XC6SLX9]
+ * KC705, a Kintex-7 devboard from Xilinx [XC7K325T]
 MiSoC is portable and support for other boards can easily be added as external
 modules.
 
@@ -36,8 +38,8 @@ modules.
   Get Migen from: https://github.com/m-labs/migen
 
 2. Install JTAG tools.
-  For Mixxeo and M1: http://urjtag.org
-  For Papilio Pro:   http://xc3sprog.sourceforge.net
+  For Mixxeo and M1:          http://urjtag.org
+  For Papilio Pro and KC705:  http://xc3sprog.sourceforge.net
 
 3. Obtain and build any required flash proxy bitstreams. Flash proxy bitstreams
   give JTAG access to a flash chip through the FPGA.
@@ -51,7 +53,7 @@ modules.
   make
   make install
 
-5. Compile and install GCC 4.5. Take gcc-core and gcc-g++ from GNU.
+5. Compile and install GCC. Take gcc-core and gcc-g++ from GNU (version 4.5 or >=4.9).
   rm -rf libstdc++-v3
   mkdir build && cd build
   ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc --disable-libssp
@@ -65,8 +67,9 @@ modules.
 
 7. Build and flash the BIOS and bitstream. Run from MiSoC:
   For Mixxeo:      ./make.py all
-  For M1:          ./make.py -p m1 -s FramebufferSoC all
-  For Papilio Pro: ./make.py -t simple all
+  For M1:          ./make.py -p m1 all
+  For Papilio Pro: ./make.py -t ppro all
+  For KC705:       ./make.py -t kc705 all
 
 8. Run a terminal program on the board's serial port at 115200 8-N-1.
   You should get the BIOS prompt.

diff --git a/targets/kc705.py b/targets/kc705.py
@@ -0,0 +1,31 @@
+from migen.fhdl.std import *
+from migen.bus import wishbone
+
+from misoclib.gensoc import GenSoC, IntegratedBIOS
+
+class BaseSoC(GenSoC, IntegratedBIOS):
+	default_platform = "kc705"
+
+	def __init__(self, platform, **kwargs):
+		GenSoC.__init__(self, platform,
+			clk_freq=156*1000000, cpu_reset_address=0,
+			**kwargs)
+		IntegratedBIOS.__init__(self)
+
+		clk200 = platform.request("clk156")
+		self.specials += Instance("IBUFGDS",
+				i_I=clk200.p,
+				i_IB=clk200.n,
+				o_O=ClockSignal()
+		)
+		self.clock_domains.cd_sys = ClockDomain()
+		self.clock_domains.cd_pwr_on = ClockDomain(reset_less=True)
+		self.comb += self.cd_pwr_on.clk.eq(self.cd_sys.clk)
+		self.cd_sys.rst.reset = 1
+		self.sync.pwr_on += self.cd_sys.rst.eq(0)
+
+		self.submodules.usermem = wishbone.SRAM(64*1024)
+		self.add_wb_slave(lambda a: a[27:29] == 2, self.usermem.bus)
+		self.add_cpu_memory_region("sdram", 0x40000000, 64*1024)
+
+default_subtarget = BaseSoC