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genlib/coding.py: binary vs. one-hot, priority coding
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from migen.fhdl.std import * | ||
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""" | ||
Encoders and decoders between binary and one-hot representation | ||
i: input (binary or one-hot) | ||
o: output (one-hot or binary) | ||
n: "none" signal (in/out), binary value is invalid | ||
""" | ||
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class Encoder(Module): | ||
def __init__(self, width): | ||
self.i = Signal(width) # one-hot | ||
self.o = Signal(max=width) # binary | ||
self.n = Signal() # invalid: none or multiple | ||
act = dict((1<<j, self.o.eq(j)) for j in range(width)) | ||
act["default"] = self.n.eq(1) | ||
self.comb += Case(self.i, act) | ||
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class PriorityEncoder(Module): | ||
def __init__(self, width): | ||
self.i = Signal(width) # one-hot, lsb has priority | ||
self.o = Signal(max=width) # binary | ||
self.n = Signal() # none | ||
act = If(0) | ||
for j in range(width): | ||
act = act.Elif(self.i[j], self.o.eq(j)) | ||
self.comb += act | ||
self.comb += self.n.eq(self.i == 0) | ||
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class Decoder(Module): | ||
def __init__(self, width): | ||
self.i = Signal(max=width) # binary | ||
self.n = Signal() # none/invalid | ||
self.o = Signal(width) # one-hot | ||
act = dict((j, self.o.eq(1<<j)) for j in range(width)) | ||
self.comb += Case(self.i, act) | ||
self.comb += If(self.n, self.o.eq(0)) | ||
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class PriorityDecoder(Decoder): | ||
pass # same | ||
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def _main(): | ||
from migen.sim.generic import Simulator, TopLevel | ||
from migen.fhdl import verilog | ||
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e = Encoder(8) | ||
print(verilog.convert(e, ios={e.i, e.o, e.n})) | ||
pe = PriorityEncoder(8) | ||
print(verilog.convert(pe, ios={pe.i, pe.o, pe.n})) | ||
d = Decoder(8) | ||
print(verilog.convert(d, ios={d.i, d.n, d.o})) | ||
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if __name__ == "__main__": | ||
_main() |