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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: 85813b3b5863
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Jun 3, 2013

  1. csr/sram: fix page_bits computation

    kennethryerson authored and Sebastien Bourdeauducq committed Jun 3, 2013
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    e5e3492 View commit details
  2. csr/sram: fix reads on high addresses when word_bits != 0

    kennethryerson authored and Sebastien Bourdeauducq committed Jun 3, 2013
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    85813b3 View commit details
Showing with 3 additions and 10 deletions.
  1. +3 −10 migen/bus/csr.py
13 changes: 3 additions & 10 deletions migen/bus/csr.py
Original file line number Diff line number Diff line change
@@ -45,13 +45,6 @@ def do_simulation(self, s):
s.wr(self.bus.we, 1)
s.wr(self.bus.dat_w, self.transaction.data)

def _compute_page_bits(nwords):
npages = (nwords - 1)//512
if npages > 0:
return bits_for(npages-1)
else:
return 0

class SRAM(Module):
def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
if isinstance(mem_or_size, Memory):
@@ -60,7 +53,7 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
csrw_per_memw = (mem.width + data_width - 1)//data_width
word_bits = log2_int(csrw_per_memw)
page_bits = log2_int(mem.depth*csrw_per_memw, False)
page_bits = log2_int((mem.depth*csrw_per_memw + 511)//512, False)
if page_bits:
self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
else:
@@ -114,10 +107,10 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
]

if self._page is None:
self.comb += port.adr.eq(self.bus.adr[word_bits:flen(port.adr)])
self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+flen(port.adr)])
else:
pv = self._page.storage
self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:flen(port.adr)-flen(pv)], pv))
self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+flen(port.adr)-flen(pv)], pv))

def get_csrs(self):
if self._page is None: