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base repository: m-labs/misoc
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compare: d2c4afe
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  • 2 commits
  • 4 files changed
  • 1 contributor

Commits on Apr 1, 2012

  1. tb/asmicon: global test bench

    Sebastien Bourdeauducq committed Apr 1, 2012
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    f5671c5 View commit details
  2. Copy the full SHA
    d2c4afe View commit details
Showing with 88 additions and 30 deletions.
  1. +4 −2 milkymist/asmicon/bankmachine.py
  2. +2 −2 milkymist/asmicon/multiplexer.py
  3. +31 −0 tb/asmicon/asmicon.py
  4. +51 −26 tb/asmicon/common.py
6 changes: 4 additions & 2 deletions milkymist/asmicon/bankmachine.py
Original file line number Diff line number Diff line change
@@ -119,11 +119,13 @@ def get_fragment(self):
for slot in self.slots]
comb += multimux(rr.grant, mux_inputs, mux_outputs)
comb += [
self.stb.eq(state == SLOT_PENDING),
self.stb.eq(
(self.slicer.bank(self.adr) == self.bankn) \
& (state == SLOT_PENDING)),
rr.ce.eq(self.ack),
self.tag.eq(rr.grant)
]
comb += [slot.process.eq((rr.grant == i) & self.stb & self.ack)
comb += [If((rr.grant == i) & self.stb & self.ack, slot.process.eq(1))
for i, slot in enumerate(self.slots)]

return Fragment(comb, sync) + rr.get_fragment()
4 changes: 2 additions & 2 deletions milkymist/asmicon/multiplexer.py
Original file line number Diff line number Diff line change
@@ -53,11 +53,11 @@ def get_fragment(self):
outputs_filtered = [self.cmd.cas_n, self.cmd.ras_n, self.cmd.we_n]
ms = multimux(rr.grant, inputs_filtered, outputs_filtered)
comb += [
self.cmd.stb.eq(stb & ((self.cmd.is_read == self.want_reads) | (self.cmd.is_write == self.want_writes))),
self.cmd.stb.eq(stb & (self.cmd.is_read == self.want_reads) & (self.cmd.is_write == self.want_writes)),
If(self.cmd.stb, *ms)
]

comb += [req.ack.eq(self.cmd.stb & self.cmd.ack & rr.grant == i)
comb += [If(self.cmd.stb & self.cmd.ack & (rr.grant == i), req.ack.eq(1))
for i, req in enumerate(self.requests)]
comb.append(rr.ce.eq(self.cmd.ack))

31 changes: 31 additions & 0 deletions tb/asmicon/asmicon.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,31 @@
from migen.fhdl.structure import *
from migen.bus.asmibus import *
from migen.sim.generic import Simulator, TopLevel
from migen.sim.icarus import Runner

from milkymist.asmicon import *

from common import sdram_phy, sdram_geom, sdram_timing, DFILogger

def my_generator():
for x in range(100):
t = TRead(x)
yield t

def main():
dut = ASMIcon(sdram_phy, sdram_geom, sdram_timing)
initiator = Initiator(dut.hub.get_port(), my_generator())
dut.finalize()

logger = DFILogger(dut.dfi)

def end_simulation(s):
s.interrupt = initiator.done

fragment = dut.get_fragment() + initiator.get_fragment() + \
logger.get_fragment() + \
Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner(keep_files=True), TopLevel("my.vcd"))
sim.run()

main()
77 changes: 51 additions & 26 deletions tb/asmicon/common.py
Original file line number Diff line number Diff line change
@@ -15,6 +15,12 @@ def ns(t, margin=True):
t += clk_period_ns/2
return ceil(t/clk_period_ns)

sdram_phy = asmicon.PhySettings(
dfi_d=64,
nphases=2,
rdphase=0,
wrphase=1
)
sdram_geom = asmicon.GeomSettings(
bank_a=2,
row_a=13,
@@ -35,40 +41,43 @@ def ns(t, margin=True):
write_time=16
)

def decode_sdram(ras_n, cas_n, we_n, bank, address):
elts = []
if not ras_n and cas_n and we_n:
elts.append("ACTIVATE")
elts.append("BANK " + str(bank))
elts.append("ROW " + str(address))
elif ras_n and not cas_n and we_n:
elts.append("READ\t")
elts.append("BANK " + str(bank))
elts.append("COL " + str(address))
elif ras_n and not cas_n and not we_n:
elts.append("WRITE\t")
elts.append("BANK " + str(bank))
elts.append("COL " + str(address))
elif ras_n and cas_n and not we_n:
elts.append("BST")
elif not ras_n and not cas_n and we_n:
elts.append("AUTO REFRESH")
elif not ras_n and cas_n and not we_n:
elts.append("PRECHARGE")
if address & 2**10:
elts.append("ALL")
else:
elts.append("BANK " + str(bank))
elif not ras_n and not cas_n and not we_n:
elts.append("LMR")
return elts

class CommandLogger:
def __init__(self, cmd, rw=False):
self.cmd = cmd
self.rw = rw

def do_simulation(self, s):
elts = ["@" + str(s.cycle_counter)]

cmdp = Proxy(s, self.cmd)
if not cmdp.ras_n and cmdp.cas_n and cmdp.we_n:
elts.append("ACTIVATE")
elts.append("BANK " + str(cmdp.ba))
elts.append("ROW " + str(cmdp.a))
elif cmdp.ras_n and not cmdp.cas_n and cmdp.we_n:
elts.append("READ\t")
elts.append("BANK " + str(cmdp.ba))
elts.append("COL " + str(cmdp.a))
elif cmdp.ras_n and not cmdp.cas_n and not cmdp.we_n:
elts.append("WRITE\t")
elts.append("BANK " + str(cmdp.ba))
elts.append("COL " + str(cmdp.a))
elif cmdp.ras_n and cmdp.cas_n and not cmdp.we_n:
elts.append("BST")
elif not cmdp.ras_n and not cmdp.cas_n and cmdp.we_n:
elts.append("AUTO REFRESH")
elif not cmdp.ras_n and cmdp.cas_n and not cmdp.we_n:
elts.append("PRECHARGE")
if cmdp.a & 2**10:
elts.append("ALL")
else:
elts.append("BANK " + str(cmdp.ba))
elif not cmdp.ras_n and not cmdp.cas_n and not cmdp.we_n:
elts.append("LMR")

elts += decode_sdram(cmdp.ras_n, cmdp.cas_n, cmdp.we_n, cmdp.ba, cmdp.a)
if len(elts) > 1:
print("\t".join(elts))

@@ -79,6 +88,22 @@ def get_fragment(self):
comb = []
return Fragment(comb, sim=[self.do_simulation])

class DFILogger:
def __init__(self, dfi):
self.dfi = dfi

def do_simulation(self, s):
dfip = Proxy(s, self.dfi)

for i, p in enumerate(dfip.phases):
elts = ["PH=" + str(i) + "\t @" + str(s.cycle_counter)]
elts += decode_sdram(p.ras_n, p.cas_n, p.we_n, p.bank, p.address)
if len(elts) > 1:
print("\t".join(elts))

def get_fragment(self):
return Fragment(sim=[self.do_simulation])

class SlotsLogger:
def __init__(self, slicer, slots):
self.slicer = slicer