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base repository: m-labs/migen
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head repository: m-labs/migen
compare: 71b89e4c46e5
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  • 5 commits
  • 6 files changed
  • 2 contributors

Commits on Jun 30, 2013

  1. coding.py: rewrite If() to make verilog more readable

    @jordens
    jordens authored and Sebastien Bourdeauducq committed Jun 30, 2013
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  2. support re-slicing and non-unit step size 

    * support slicing of Slice/Cat/Replicate through lowering
* support non-unit step size slices through unpacking and Cat()
    @jordens
    jordens authored and Sebastien Bourdeauducq committed Jun 30, 2013
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  3. genlib/misc: remove bitreverse

    Sebastien Bourdeauducq committed Jun 30, 2013
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  4. fhdl/tools: separate complex slice lowerer from basic lowerer

    Sebastien Bourdeauducq committed Jun 30, 2013
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  5. fhdl/verilog: lower complex slices before reset insertion

    Sebastien Bourdeauducq committed Jun 30, 2013
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