Framebuffer mixing

m-labs · May 10, 2013 · e96b027 · e96b027
1 parent 3ab83fb
commit e96b027
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Showing 6 changed files with 93 additions and 11 deletions.
diff --git a/milkymist/dvisampler/debug.py b/milkymist/dvisampler/debug.py
@@ -41,6 +41,6 @@ def __init__(self, pads, asmiport):
 			self.packer.sink.stb.eq(fifo.readable),
 			fifo.re.eq(self.packer.sink.ack),
 			self.packer.sink.payload.word.eq(fifo.dout),
-			self.packer.source.connect(self.cast.sink, match_by_position=True),
-			self.cast.source.connect(self.dma.data, match_by_position=True)
+			self.packer.source.connect_flat(self.cast.sink),
+			self.cast.source.connect_flat(self.dma.data)
 		]
diff --git a/milkymist/framebuffer/__init__.py b/milkymist/framebuffer/__init__.py
@@ -1,7 +1,8 @@
 from migen.fhdl.structure import *
 from migen.fhdl.module import Module
+from migen.flow.actor import *
 from migen.flow.network import *
-from migen.bank.description import CSRStorage
+from migen.bank.description import CSRStorage, AutoCSR
 from migen.actorlib import dma_asmi, structuring, sim, spi
 
 from milkymist.framebuffer.lib import bpp, pixel_layout, dac_layout, FrameInitiator, VTG, FIFO
@@ -50,3 +51,76 @@ def __init__(self, pads, asmiport, simulation=False):
 
 	def get_csrs(self):
 		return [self._enable] + self._fi.get_csrs() + self._dma.get_csrs()
+
+class Blender(PipelinedActor, AutoCSR):
+	def __init__(self, nimages, latency):
+		self.sink = Sink([("i"+str(i), pixel_layout) for i in range(nimages)])
+		self.source = Source(pixel_layout)
+		factors = []
+		for i in range(nimages):
+			name = "f"+str(i)
+			csr = CSRStorage(8, name=name)
+			setattr(self, name, csr)
+			factors.append(csr.storage)
+		PipelinedActor.__init__(self, latency)
+
+		###
+
+		imgs = [getattr(self.sink.payload, "i"+str(i)) for i in range(nimages)]
+		outval = Record(pixel_layout)
+		for e in pixel_layout:
+			name = e[0]
+			inpixs = [getattr(img, name) for img in imgs]
+			outpix = getattr(outval, name)
+			for component in ["r", "g", "b"]:
+				incomps = [getattr(pix, component) for pix in inpixs]
+				outcomp = getattr(outpix, component)
+				self.comb += outcomp.eq(sum(incomp*factor for incomp, factor in zip(incomps, factors)) >> 8)
+
+		pipe_stmts = []
+		for i in range(latency):
+			new_outval = Record(pixel_layout)
+			pipe_stmts.append(new_outval.eq(outval))
+			outval = new_outval
+		self.sync += If(self.pipe_ce, pipe_stmts)
+		self.comb += self.source.payload.eq(outval)
+
+class MixFramebuffer(Module, AutoCSR):
+	def __init__(self, pads, *asmiports, blender_latency=3):
+		pack_factor = asmiports[0].hub.dw//(2*bpp)
+		packed_pixels = structuring.pack_layout(pixel_layout, pack_factor)
+
+		self._enable = CSRStorage()
+		self.fi = FrameInitiator()
+		self.blender = Blender(len(asmiports), blender_latency)
+		self.comb += self.fi.trigger.eq(self._enable.storage)
+
+		g = DataFlowGraph()
+		for n, asmiport in enumerate(asmiports):
+			dma = spi.DMAReadController(dma_asmi.Reader(asmiport), spi.MODE_EXTERNAL, length_reset=640*480*4)
+			cast = structuring.Cast(asmiport.hub.dw, packed_pixels, reverse_to=True)
+			unpack = structuring.Unpack(pack_factor, pixel_layout)
+
+			g.add_connection(dma, cast)
+			g.add_connection(cast, unpack)
+			g.add_connection(unpack, self.blender, sink_subr=["i"+str(n)+"/p0", "i"+str(n)+"/p1"])
+
+			self.comb += dma.generator.trigger.eq(self._enable.storage)
+			setattr(self, "dma"+str(n), dma)
+
+		vtg = VTG()
+		fifo = FIFO()
+		g.add_connection(self.fi, vtg, sink_ep="timing")
+		g.add_connection(self.blender, vtg, sink_ep="pixels")
+		g.add_connection(vtg, fifo)
+		self.submodules += CompositeActor(g)
+
+		self.comb += [
+			pads.hsync_n.eq(fifo.vga_hsync_n),
+			pads.vsync_n.eq(fifo.vga_vsync_n),
+			pads.r.eq(fifo.vga_r),
+			pads.g.eq(fifo.vga_g),
+			pads.b.eq(fifo.vga_b),
+			pads.psave_n.eq(1)
+		]
+
diff --git a/software/videomixer/Makefile b/software/videomixer/Makefile
@@ -32,12 +32,12 @@ main.o: main.c
 
 define gen0
 @echo " GEN " $@
-@sed -e "s/dvisamplerX/dvisampler0/g;s/DVISAMPLERX/DVISAMPLER0/g" $< > $@
+@sed -e "s/dvisamplerX/dvisampler0/g;s/DVISAMPLERX/DVISAMPLER0/g;s/fb_dmaX/fb_dma0/g" $< > $@
 endef
 
 define gen1
 @echo " GEN " $@
-@sed -e "s/dvisamplerX/dvisampler1/g;s/DVISAMPLERX/DVISAMPLER1/g" $< > $@
+@sed -e "s/dvisamplerX/dvisampler1/g;s/DVISAMPLERX/DVISAMPLER1/g;s/fb_dmaX/fb_dma1/g" $< > $@
 endef
 
 dvisampler0.c: dvisamplerX.c

diff --git a/software/videomixer/dvisamplerX.c b/software/videomixer/dvisamplerX.c
@@ -35,7 +35,7 @@ void dvisamplerX_isr(void)
 	}
 
 	if(fb_index != -1)
-		fb_base_write((unsigned int)dvisamplerX_framebuffers[fb_index]);
+		fb_dmaX_base_write((unsigned int)dvisamplerX_framebuffers[fb_index]);
 }
 
 void dvisamplerX_init_video(void)
@@ -57,7 +57,7 @@ void dvisamplerX_init_video(void)
 	dvisamplerX_dma_slot1_status_write(DVISAMPLER_SLOT_LOADED);
 	dvisamplerX_next_fb_index = 2;
 
-	fb_base_write((unsigned int)dvisamplerX_framebuffers[3]);
+	fb_dmaX_base_write((unsigned int)dvisamplerX_framebuffers[3]);
 }
 
 static int dvisamplerX_d0, dvisamplerX_d1, dvisamplerX_d2;

diff --git a/software/videomixer/main.c b/software/videomixer/main.c
@@ -21,8 +21,14 @@ int main(void)
 	timer0_en_write(1);
 
 	dvisampler0_init_video();
+	dvisampler1_init_video();
 	fb_enable_write(1);
-	while(1) dvisampler0_service();
+	fb_blender_f0_write(127);
+	fb_blender_f1_write(127);
+	while(1) {
+		dvisampler0_service();
+		dvisampler1_service();
+	}
 
 	return 0;
 }
diff --git a/top.py b/top.py
@@ -93,8 +93,10 @@ def __init__(self, platform):
 		#
 		self.submodules.asmicon = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
 		asmiport_wb = self.asmicon.hub.get_port()
-		asmiport_fb = self.asmicon.hub.get_port(3)
+		asmiport_fb0 = self.asmicon.hub.get_port(2)
+		asmiport_fb1 = self.asmicon.hub.get_port(2)
 		asmiport_dvi0 = self.asmicon.hub.get_port(2)
+		asmiport_dvi1 = self.asmicon.hub.get_port(2)
 		self.asmicon.finalize()
 
 		#
@@ -142,10 +144,10 @@ def __init__(self, platform):
 		self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
 		self.submodules.identifier = identifier.Identifier(0x4D31, version, int(clk_freq))
 		self.submodules.timer0 = timer.Timer()
-		self.submodules.fb = framebuffer.Framebuffer(platform.request("vga"), asmiport_fb)
+		self.submodules.fb = framebuffer.MixFramebuffer(platform.request("vga"), asmiport_fb0, asmiport_fb1)
 		self.submodules.asmiprobe = asmiprobe.ASMIprobe(self.asmicon.hub)
 		self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), asmiport_dvi0)
-		#self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1))
+		self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), asmiport_dvi1)
 
 		self.submodules.csrbankarray = csrgen.BankArray(self,
 			lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])