uart/sim: add pty (optional, to use flterm)

m-labs · Mar 9, 2015 · b157031 · b157031
1 parent 6cbf130
commit b157031
Showing 1 changed file with 13 additions and 0 deletions.
diff --git a/misoclib/com/uart/phy/sim.py b/misoclib/com/uart/phy/sim.py
@@ -1,3 +1,5 @@
+import os, pty, time
+
 from migen.fhdl.std import *
 from migen.flow.actor import Sink, Source
 
@@ -15,3 +17,14 @@ def __init__(self, pads, *args, **kwargs):
 			self.source.data.eq(pads.sink_data),
 			pads.sink_ack.eq(self.source.ack)
 		]
+
+		m, s = pty.openpty()
+		name = os.ttyname(s)
+		print("UART tty: "+name)
+		time.sleep(0.5) # pause for user
+		f = open("/tmp/simserial", "w")
+		f.write(os.ttyname(s))
+		f.close()
+
+	def do_exit(self, *args, **kwargs):
+		os.remove("/tmp/simserial")