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base repository: m-labs/migen
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compare: 6a979a802351
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  • 2 commits
  • 26 files changed
  • 1 contributor

Commits on Mar 13, 2015

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    702d177 View commit details
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    6a979a8 View commit details
12 changes: 6 additions & 6 deletions examples/cordic/cordic_impl.py
Original file line number Diff line number Diff line change
@@ -5,8 +5,7 @@
from migen.genlib.cordic import Cordic
from mibuild.tools import mkdir_noerror
from mibuild.generic_platform import *
from mibuild.crg import SimpleCRG
from mibuild.xilinx.ise import XilinxISEPlatform
from mibuild.xilinx import XilinxPlatform

class CordicImpl(Module):
def __init__(self, name, **kwargs):
@@ -27,19 +26,20 @@ def __init__(self, name, **kwargs):
def build(self):
self.platform.build(self, build_name=self.name)

class Platform(XilinxISEPlatform):
class Platform(XilinxPlatform):
default_clk_name = "clk"
default_clk_period = 20.0

_io = [
("clk", 0, Pins("AB13")),
("rst", 0, Pins("V5")),
("do", 0,
Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3",
"U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4",
"M5 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1"),
),
]
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", self._io,
lambda p: SimpleCRG(p, "clk", "rst"))
XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", self._io)

if __name__ == "__main__":
default = dict(width=16, guard=0, eval_mode="pipelined",
1 change: 1 addition & 0 deletions mibuild/altera/quartus.py
Original file line number Diff line number Diff line change
@@ -94,5 +94,6 @@ def build(self, fragment, build_dir="build", build_name="top",
return vns

def add_period_constraint(self, clk, period):
# TODO: handle differential clk
self.add_platform_command("""set_global_assignment -name DUTY_CYCLE 50 -section_id {clk}""", clk=clk)
self.add_platform_command("""set_global_assignment -name FMAX_REQUIREMENT "{freq} MHz" -section_id {clk}\n""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
14 changes: 0 additions & 14 deletions mibuild/crg.py

This file was deleted.

25 changes: 17 additions & 8 deletions mibuild/generic_platform.py
Original file line number Diff line number Diff line change
@@ -3,6 +3,7 @@
from migen.fhdl.std import *
from migen.fhdl.structure import _Fragment
from migen.genlib.record import Record
from migen.genlib.io import CRG
from migen.fhdl import verilog, edif
from migen.util.misc import autotype

@@ -177,10 +178,9 @@ def get_platform_commands(self):
return self.platform_commands

class GenericPlatform:
def __init__(self, device, io, default_crg_factory=None, connectors=[], name=None):
def __init__(self, device, io, connectors=[], name=None):
self.device = device
self.constraint_manager = ConstraintManager(io, connectors)
self.default_crg_factory = default_crg_factory
if name is None:
name = self.__module__.split(".")[-1]
self.name = name
@@ -194,6 +194,9 @@ def request(self, *args, **kwargs):
def lookup_request(self, *args, **kwargs):
return self.constraint_manager.lookup_request(*args, **kwargs)

def add_period_constraint(self, clk, period):
raise NotImplementedError

def add_platform_command(self, *args, **kwargs):
return self.constraint_manager.add_platform_command(*args, **kwargs)

@@ -205,17 +208,20 @@ def finalize(self, fragment, *args, **kwargs):
raise ConstraintError("Already finalized")
# if none exists, create a default clock domain and drive it
if not fragment.clock_domains:
if self.default_crg_factory is None:
raise NotImplementedError("No clock/reset generator defined by either platform or user")
crg = self.default_crg_factory(self)
if not hasattr(self, "default_clk_name"):
raise NotImplementedError("No default clock and no clock domain defined")
crg = CRG(self.request(self.default_clk_name))
fragment += crg.get_fragment()
self.do_finalize(fragment, *args, **kwargs)
self.finalized = True

def do_finalize(self, fragment, *args, **kwargs):
"""overload this and e.g. add_platform_command()'s after the
modules had their say"""
pass
"""overload this and e.g. add_platform_command()'s after the modules had their say"""
if hasattr(self, "default_clk_period"):
try:
self.add_period_constraint(self.lookup_request(self.default_clk_name), self.default_clk_period)
except ConstraintError:
pass

def add_source(self, filename, language=None):
if language is None:
@@ -285,3 +291,6 @@ def build_cmdline(self, *args, **kwargs):
argdict = dict((k, autotype(v)) for k, v in zip(*[iter(arg)]*2))
kwargs.update(argdict)
self.build(*args, **kwargs)

def create_programmer(self):
raise NotImplementedError
15 changes: 4 additions & 11 deletions mibuild/platforms/apf27.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
from mibuild.generic_platform import *
from mibuild.crg import SimpleCRG
from mibuild.xilinx.ise import XilinxISEPlatform
from mibuild.xilinx import XilinxPlatform

_ios = [
("clk0", 0, Pins("N9"), IOStandard("LVCMOS18")),
@@ -141,15 +140,9 @@
"None") # 116 USBH2_CLK USB_HOST2 +2V5 PA0
]

class Platform(XilinxISEPlatform):
class Platform(XilinxPlatform):
default_clk_name = "clk0"
default_clk_period = 10
def __init__(self):
XilinxISEPlatform.__init__(self, "xc3s200a-ft256-4", _ios,
lambda p: SimpleCRG(p, "clk0", None), _connectors)

def do_finalize(self, fragment):
try:
self.add_period_constraint(self.lookup_request("clk0"), 10)
except ConstraintError:
pass
def __init__(self):
XilinxPlatform.__init__(self, "xc3s200a-ft256-4", _ios, _connectors)
16 changes: 4 additions & 12 deletions mibuild/platforms/apf51.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
from mibuild.generic_platform import *
from mibuild.crg import SimpleCRG
from mibuild.xilinx.ise import XilinxISEPlatform
from mibuild.xilinx import XilinxPlatform

_ios = [
("clk3", 0, Pins("N8"), IOStandard("LVCMOS33")),
@@ -168,16 +167,9 @@
"None") # 140 FPGA_BANK3_POWER
]

class Platform(XilinxISEPlatform):
class Platform(XilinxPlatform):
default_clk_name = "clk3"
default_clk_period = 10.526
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx9-2csg225", _ios,
lambda p: SimpleCRG(p, "clk3", None), _connectors)

def do_finalize(self, fragment):
try:
self.add_period_constraint(self.lookup_request("clk3"), 10.526)
except ConstraintError:
pass

def __init__(self):
XilinxPlatform.__init__(self, "xc6slx9-2csg225", _ios, _connectors)
11 changes: 2 additions & 9 deletions mibuild/platforms/de0nano.py
Original file line number Diff line number Diff line change
@@ -2,7 +2,6 @@
# License: BSD

from mibuild.generic_platform import *
from mibuild.crg import SimpleCRG
from mibuild.altera.quartus import AlteraQuartusPlatform
from mibuild.altera.programmer import USBBlaster

@@ -94,15 +93,9 @@
class Platform(AlteraQuartusPlatform):
default_clk_name = "clk50"
default_clk_period = 20

def __init__(self):
AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io,
lambda p: SimpleCRG(p, "clk50", None))
AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io)

def create_programmer(self):
return USBBlaster()

def do_finalize(self, fragment):
try:
self.add_period_constraint(self.lookup_request("clk50"), 20)
except ConstraintError:
pass
78 changes: 32 additions & 46 deletions mibuild/platforms/kc705.py
Original file line number Diff line number Diff line change
@@ -1,9 +1,6 @@
from mibuild.generic_platform import *
from mibuild.crg import SimpleCRG
from mibuild.xilinx.common import CRG_DS
from mibuild.xilinx.ise import XilinxISEPlatform
from mibuild.xilinx.vivado import XilinxVivadoPlatform
from mibuild.xilinx.programmer import XC3SProg, VivadoProgrammer
from mibuild.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
from mibuild.xilinx.ise import XilinxISEToolchain

_io = [
("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
@@ -378,47 +375,36 @@
)
]

def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
if toolchain == "ise":
xilinx_platform = XilinxISEPlatform
elif toolchain == "vivado":
xilinx_platform = XilinxVivadoPlatform
else:
raise ValueError
class Platform(XilinxPlatform):
identifier = 0x4B37
default_clk_name = "clk156"
default_clk_period = 6.4

class RealPlatform(xilinx_platform):
identifier = 0x4B37
default_clk_name = "clk156"
default_clk_period = 6.4
bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
def __init__(self, toolchain="vivado", programmer="xc3sprog"):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors,
toolchain=toolchain)
self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
self.programmer = programmer

def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):
xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory, _connectors)
def create_programmer(self):
if self.programmer == "xc3sprog":
return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
elif self.programmer == "vivado":
return VivadoProgrammer()
else:
raise ValueError("{} programmer is not supported".format(programmer))

def create_programmer(self):
if programmer == "xc3sprog":
return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
elif programmer == "vivado":
return VivadoProgrammer()
else:
raise ValueError("{} programmer is not supported".format(programmer))

def do_finalize(self, fragment):
try:
self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
except ConstraintError:
pass
if isinstance(self, XilinxISEPlatform):
self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
else:
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")

return RealPlatform(*args, **kwargs)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
except ConstraintError:
pass
if isinstance(self.toolchain, XilinxISEToolchain):
self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
else:
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
24 changes: 10 additions & 14 deletions mibuild/platforms/lx9_microboard.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
from mibuild.generic_platform import *
from mibuild.crg import SimpleCRG
from mibuild.xilinx.ise import XilinxISEPlatform
from mibuild.xilinx import XilinxPlatform

_io = [
("user_btn", 0, Pins("V4"), IOStandard("LVCMOS33"),
@@ -102,25 +101,22 @@
]


class Platform(XilinxISEPlatform):
class Platform(XilinxPlatform):
default_clk_name = "clk_y3"
default_clk_period = 10
bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
ise_commands = """
promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
"""

def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx9-2csg324", _io,
lambda p: SimpleCRG(p, "clk_y3", "user_btn"))
XilinxPlatform.__init__(self, "xc6slx9-2csg324", _io)
self.add_platform_command("""
CONFIG VCCAUX = "3.3";
""")
self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
self.ise_commands = """
promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
"""

def do_finalize(self, fragment):
try:
self.add_period_constraint(self.lookup_request("clk_y3"), 10)
except ConstraintError:
pass
XilinxPlatform.do_finalize(self, fragment)

try:
eth_clocks = self.lookup_request("eth_clocks")
@@ -130,5 +126,5 @@ def do_finalize(self, fragment):
TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns;
TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns;
""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx)
except ContraintError:
except ConstraintError:
pass
14 changes: 5 additions & 9 deletions mibuild/platforms/m1.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
from mibuild.generic_platform import *
from mibuild.crg import SimpleCRG
from mibuild.xilinx.ise import XilinxISEPlatform
from mibuild.xilinx import XilinxPlatform
from mibuild.xilinx.programmer import UrJTAG

_io = [
@@ -118,22 +117,19 @@
)
]

class Platform(XilinxISEPlatform):
class Platform(XilinxPlatform):
identifier = 0x4D31
default_clk_name = "clk50"
default_clk_period = 20

def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
lambda p: SimpleCRG(p, "clk50", None))
XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io)

def create_programmer(self):
return UrJTAG("fjmem-m1.bit")

def do_finalize(self, fragment):
try:
self.add_period_constraint(self.lookup_request("clk50"), 20)
except ConstraintError:
pass
XilinxPlatform.do_finalize(self, fragment)

try:
eth_clocks = self.lookup_request("eth_clocks")
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