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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: d09529d48305
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Mar 13, 2015

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    32676ff View commit details
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    d09529d View commit details
Showing with 2 additions and 24 deletions.
  1. +2 −2 misoclib/soc/sdram.py
  2. +0 −22 targets/simple.py
4 changes: 2 additions & 2 deletions misoclib/soc/sdram.py
Original file line number Diff line number Diff line change
@@ -53,8 +53,8 @@ def register_sdram_phy(self, phy, sdram_geom, sdram_timing):
# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
# Remove this workaround when fixed by Xilinx.
from mibuild.xilinx.vivado import XilinxVivadoPlatform
if isinstance(self.platform, XilinxVivadoPlatform):
from mibuild.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master()))
else:
22 changes: 0 additions & 22 deletions targets/simple.py
Original file line number Diff line number Diff line change
@@ -1,39 +1,17 @@
from migen.fhdl.std import *
from migen.bus import wishbone
from migen.genlib.io import DifferentialInput

from misoclib.soc import SoC, mem_decoder
from misoclib.com.liteeth.phy import LiteEthPHY
from misoclib.com.liteeth.mac import LiteEthMAC

class _CRG(Module):
def __init__(self, clk_crg):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)

# Power on Reset (vendor agnostic)
rst_n = Signal()
self.sync.por += rst_n.eq(1)
self.comb += [
self.cd_sys.clk.eq(clk_crg),
self.cd_por.clk.eq(clk_crg),
self.cd_sys.rst.eq(~rst_n)
]

class BaseSoC(SoC):
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
clk_freq=int((1/(platform.default_clk_period))*1000000000),
with_rom=True,
with_sdram=True, sdram_size=16*1024,
**kwargs)
clk_in = platform.request(platform.default_clk_name)
clk_crg = Signal()
if hasattr(clk_in, "p"):
self.specials += DifferentialInput(clk_in.p, clk_in.n, clk_crg)
else:
self.comb += clk_crg.eq(clk_in)
self.submodules.crg = _CRG(clk_crg)

class MiniSoC(BaseSoC):
csr_map = {