soc: rename with_sdram option to with_main_ram (with_sdram was confus…

…ing)
m-labs · Mar 13, 2015 · 28d04ec · sbourdeauducq · Mar 21, 2015 · enjoy-digital
1 parent d09529d
commit 28d04ec
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Showing 8 changed files with 19 additions and 18 deletions.
diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
@@ -39,7 +39,7 @@ def __init__(self, platform, clk_freq, cpu_or_bridge=None,
 							   cpu_boot_file="software/bios/bios.bin",
 				with_rom=False, rom_size=0x8000,
 				with_sram=True, sram_size=4096,
-				with_sdram=False, sdram_size=64*1024,
+				with_main_ram=False, main_ram_size=64*1024,
 				with_csr=True, csr_data_width=8, csr_address_width=14,
 				with_uart=True, uart_baudrate=115200,
 				with_identifier=True,
@@ -62,8 +62,8 @@ def __init__(self, platform, clk_freq, cpu_or_bridge=None,
 		self.with_sram = with_sram
 		self.sram_size = sram_size
 
-		self.with_sdram = with_sdram
-		self.sdram_size = sdram_size
+		self.with_main_ram = with_main_ram
+		self.main_ram_size = main_ram_size
 
 		self.with_uart = with_uart
 		self.uart_baudrate = uart_baudrate
@@ -98,9 +98,10 @@ def __init__(self, platform, clk_freq, cpu_or_bridge=None,
 				self.submodules.sram = wishbone.SRAM(sram_size)
 				self.register_mem("sram", self.mem_map["sram"], self.sram.bus, sram_size)
 
-			if with_sdram:
-				self.submodules.sdram = wishbone.SRAM(sdram_size)
-				self.register_mem("sdram", self.mem_map["sdram"], self.sdram.bus, sdram_size)
+			# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
+			if with_main_ram:
+				self.submodules.main_ram = wishbone.SRAM(main_ram_size)
+				self.register_mem("sdram", self.mem_map["sdram"], self.main_ram.bus, main_ram_size)
 
 		elif cpu_or_bridge is not None and not isinstance(cpu_or_bridge, CPU):
 			self._wb_masters += [cpu_or_bridge.wishbone]

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
@@ -60,25 +60,25 @@ def register_sdram_phy(self, phy, sdram_geom, sdram_timing):
 				else:
 					self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())
 				lasmic = self.sdram.controller.lasmic
-				sdram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
-				self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, sdram_size)
+				main_ram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
+				self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, main_ram_size)
 
 		# MINICON frontend
 		elif self.ramcon_type == "minicon":
 			sdram_width = flen(self.sdram.controller.bus.dat_r)
-			sdram_size = 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8
+			main_ram_size = 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8
 
 			if sdram_width == 32:
-				self.register_mem("sdram", self.mem_map["sdram"], self.sdram.controller.bus, sdram_size)
+				self.register_mem("sdram", self.mem_map["sdram"], self.sdram.controller.bus, main_ram_size)
 			elif sdram_width < 32:
 				self.submodules.downconverter = downconverter = wishbone.DownConverter(32, sdram_width)
 				self.comb += Record.connect(downconverter.wishbone_o, self.sdram.controller.bus)
-				self.register_mem("sdram", self.mem_map["sdram"], downconverter.wishbone_i, sdram_size)
+				self.register_mem("sdram", self.mem_map["sdram"], downconverter.wishbone_i, main_ram_size)
 			else:
 				raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
 
 	def do_finalize(self):
-		if not self.with_sdram:
+		if not self.with_main_ram:
 			if not self._sdram_phy_registered:
 				raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
 		SoC.do_finalize(self)
diff --git a/targets/de0nano.py b/targets/de0nano.py
@@ -89,7 +89,7 @@ def __init__(self, platform, **kwargs):
 
 		self.submodules.crg = _CRG(platform)
 
-		if not self.with_sdram:
+		if not self.with_main_ram:
 			sdram_geom = sdram.GeomSettings(
 				bank_a=2,
 				row_a=13,

diff --git a/targets/kc705.py b/targets/kc705.py
@@ -80,7 +80,7 @@ def __init__(self, platform, **kwargs):
 
 		self.submodules.crg = _CRG(platform)
 
-		if not self.with_sdram:
+		if not self.with_main_ram:
 			sdram_geom = sdram.GeomSettings(
 				bank_a=3,
 				row_a=16,

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
@@ -40,7 +40,7 @@ def __init__(self, platform, **kwargs):
 
 		self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
 
-		if not self.with_sdram:
+		if not self.with_main_ram:
 			sdram_geom = sdram.GeomSettings(
 				bank_a=2,
 				row_a=13,

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
@@ -96,7 +96,7 @@ def __init__(self, platform, **kwargs):
 
 		self.submodules.crg = _CRG(platform, clk_freq)
 
-		if not self.with_sdram:
+		if not self.with_main_ram:
 			sdram_geom = sdram.GeomSettings(
 				bank_a=2,
 				row_a=13,

diff --git a/targets/ppro.py b/targets/ppro.py
@@ -73,7 +73,7 @@ def __init__(self, platform, **kwargs):
 
 		self.submodules.crg = _CRG(platform, clk_freq)
 
-		if not self.with_sdram:
+		if not self.with_main_ram:
 			sdram_geom = sdram.GeomSettings(
 				bank_a=2,
 				row_a=12,

diff --git a/targets/simple.py b/targets/simple.py
@@ -10,7 +10,7 @@ def __init__(self, platform, **kwargs):
 		SoC.__init__(self, platform,
 			clk_freq=int((1/(platform.default_clk_period))*1000000000),
 			with_rom=True,
-			with_sdram=True, sdram_size=16*1024,
+			with_main_ram=True, main_ram_size=16*1024,
 			**kwargs)
 
 class MiniSoC(BaseSoC):