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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: d52ecc374068
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Mar 9, 2015

  1. Copy the full SHA
    f7b3126 View commit details
  2. liteeth: do not insert CRC/Preamble in simulation to allow direct con…

    …nection to ethernet tap
    root committed Mar 9, 2015
    Copy the full SHA
    d52ecc3 View commit details
Showing with 7 additions and 3 deletions.
  1. +5 −1 misoclib/com/liteeth/mac/core/__init__.py
  2. +2 −2 misoclib/com/liteeth/mac/frontend/sram.py
6 changes: 5 additions & 1 deletion misoclib/com/liteeth/mac/core/__init__.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.mac.core import gap, preamble, crc, padding, last_be
from misoclib.com.liteeth.phy.sim import LiteEthPHYSim

class LiteEthMACCore(Module, AutoCSR):
def __init__(self, phy, dw, endianness="big", with_hw_preamble_crc=True):
@@ -20,8 +21,11 @@ def __init__(self, phy, dw, endianness="big", with_hw_preamble_crc=True):
rx_pipeline += [rx_gap_checker]

# Preamble / CRC
if with_hw_preamble_crc:
if isinstance(phy, LiteEthPHYSim):
# In simulation, avoid CRC/Preamble to enable direct connection
# to the Ethernet tap.
self._hw_preamble_crc = CSRStatus(reset=1)
elif with_hw_preamble_crc:
# Preamble insert/check
preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)
4 changes: 2 additions & 2 deletions misoclib/com/liteeth/mac/frontend/sram.py
Original file line number Diff line number Diff line change
@@ -69,10 +69,10 @@ def __init__(self, dw, depth, nslots=2):
self.submodules += fsm

fsm.act("IDLE",
inc_cnt.eq(sink.stb),
If(sink.stb & sink.sop,
ongoing.eq(1),
If(fifo.sink.ack,
ongoing.eq(1),
inc_cnt.eq(1),
NextState("WRITE")
)
)