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base repository: m-labs/misoc
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  • 3 commits
  • 4 files changed
  • 1 contributor

Commits on Mar 12, 2015

  1. uart/liteeth: only import the phy we are going to use (UARTPHYSim can…

    …not be imported on Windows since based on pty).
    enjoy-digital committed Mar 12, 2015
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    767d457 View commit details
  2. soc/sdram: add workaround for Vivado issue with our L2 cache, reporte…

    …d to Xilinx in november 2014, remove it when fixed by Xilinx
    enjoy-digital committed Mar 12, 2015
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    cd6c04b View commit details
  3. 6
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    f18ae9b View commit details
Showing with 28 additions and 12 deletions.
  1. +3 −4 misoclib/com/liteeth/phy/__init__.py
  2. +2 −3 misoclib/com/uart/phy/__init__.py
  3. +9 −1 misoclib/soc/sdram.py
  4. +14 −4 targets/simple.py
7 changes: 3 additions & 4 deletions misoclib/com/liteeth/phy/__init__.py
Original file line number Diff line number Diff line change
@@ -1,17 +1,16 @@
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *

from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
from misoclib.com.liteeth.phy.mii import LiteEthPHYMII
from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII

def LiteEthPHY(clock_pads, pads, **kwargs):
# Autodetect PHY
if hasattr(pads, "source_stb"):
from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
return LiteEthPHYSim(pads)
elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8:
from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
return LiteEthPHYGMII(clock_pads, pads, **kwargs)
elif flen(pads.tx_data) == 4:
from misoclib.com.liteeth.phy.mii import LiteEthPHYMII
return LiteEthPHYMII(clock_pads, pads, **kwargs)
else:
raise ValueError("Unable to autodetect PHY from platform file, use direct instanciation")
5 changes: 2 additions & 3 deletions misoclib/com/uart/phy/__init__.py
Original file line number Diff line number Diff line change
@@ -1,12 +1,11 @@
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *

from misoclib.com.uart.phy.sim import UARTPHYSim
from misoclib.com.uart.phy.serial import UARTPHYSerial

def UARTPHY(pads, *args, **kwargs):
# Autodetect PHY
if hasattr(pads, "source_stb"):
from misoclib.com.uart.phy.sim import UARTPHYSim
return UARTPHYSim(pads, *args, **kwargs)
else:
from misoclib.com.uart.phy.serial import UARTPHYSerial
return UARTPHYSerial(pads, *args, **kwargs)
10 changes: 9 additions & 1 deletion misoclib/soc/sdram.py
Original file line number Diff line number Diff line change
@@ -50,7 +50,15 @@ def register_sdram_phy(self, phy, sdram_geom, sdram_timing):
self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())

if self.with_l2:
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())
# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
# Remove this workaround when fixed by Xilinx.
from mibuild.xilinx.vivado import XilinxVivadoPlatform
if isinstance(self.platform, XilinxVivadoPlatform):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master()))
else:
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())
lasmic = self.sdram.controller.lasmic
sdram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, sdram_size)
18 changes: 14 additions & 4 deletions targets/simple.py
Original file line number Diff line number Diff line change
@@ -6,16 +6,16 @@
from misoclib.com.liteeth.mac import LiteEthMAC

class _CRG(Module):
def __init__(self, clk_in):
def __init__(self, clk_crg):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)

# Power on Reset (vendor agnostic)
rst_n = Signal()
self.sync.por += rst_n.eq(1)
self.comb += [
self.cd_sys.clk.eq(clk_in),
self.cd_por.clk.eq(clk_in),
self.cd_sys.clk.eq(clk_crg),
self.cd_por.clk.eq(clk_crg),
self.cd_sys.rst.eq(~rst_n)
]

@@ -27,7 +27,17 @@ def __init__(self, platform, **kwargs):
with_sdram=True, sdram_size=16*1024,
**kwargs)
clk_in = platform.request(platform.default_clk_name)
self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p)
clk_crg = Signal()
if hasattr(clk_in, "p"):
from mibuild.xilinx.vivado import XilinxVivadoPlatform
from mibuild.xilinx.ise import XilinxISEPlatform
if isinstance(platform, (XilinxISEPlatform, XilinxVivadoPlatform)):
self.specials += Instance("IBUFDS", i_I=clk_in.p, i_IB=clk_in.n, o_O=clk_crg)
else:
raise NotImplementedError
else:
self.comb += clk_crg.eq(clk_in)
self.submodules.crg = _CRG(clk_crg)

class MiniSoC(BaseSoC):
csr_map = {