m-labs · Jul 11, 2013 · Jul 11, 2013 · Jul 11, 2013
Showing with 85 additions and 11 deletions.

+5 −4 make.py

+65 −2 milkymist/memtest/__init__.py

+15 −5 top.py
diff --git a/make.py b/make.py
@@ -7,10 +7,10 @@
 from milkymist import cif
 import top, jtag
 
-def build(platform_name, build_bitstream, build_header):
+def build(platform_name, build_bitstream, build_header, *soc_args, **soc_kwargs):
 	platform_module = importlib.import_module("mibuild.platforms."+platform_name)
 	platform = platform_module.Platform()
-	soc = top.SoC(platform, platform_name)
+	soc = top.SoC(platform, platform_name, *soc_args, **soc_kwargs)
 
 	platform.add_platform_command("""
 INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
@@ -56,12 +56,13 @@ def main():
 	parser = argparse.ArgumentParser(description="milkymist-ng - a high performance SoC built on Migen technology.")
 	parser.add_argument("-p", "--platform", default="mixxeo", help="platform to build for")
 	parser.add_argument("-B", "--no-bitstream", default=False, action="store_true", help="do not build bitstream file")
-	parser.add_argument("-H", "--no-header", default=False, action="store_true", help="do not build C header file with CSR/IRQ/SDRAM_PHY defs")
+	parser.add_argument("-H", "--no-header", default=False, action="store_true", help="do not build C header files with CSR/IRQ/SDRAM_PHY defs")
 	parser.add_argument("-l", "--load", default=False, action="store_true", help="load bitstream to SRAM")
 	parser.add_argument("-f", "--flash", default=False, action="store_true", help="load bitstream to flash")
+	parser.add_argument("-m", "--with-memtest", default=False, action="store_true", help="include memtest cores")
 	args = parser.parse_args()
 
-	build(args.platform, not args.no_bitstream, not args.no_header)
+	build(args.platform, not args.no_bitstream, not args.no_header, args.with_memtest)
 	if args.load:
 		jtag.load("build/soc-"+args.platform+".bit")
 	if args.flash:

diff --git a/milkymist/memtest/__init__.py b/milkymist/memtest/__init__.py
@@ -1,10 +1,13 @@
 from migen.fhdl.std import *
 from migen.genlib.misc import optree
-from migen.fhdl import verilog
+from migen.bank.description import *
+from migen.actorlib import dma_lasmi
+from migen.actorlib.spi import MODE_SINGLE_SHOT, DMAReadController, DMAWriteController
 
 class LFSR(Module):
 	def __init__(self, n_out, n_state=31, taps=[27, 30]):
 		self.ce = Signal()
+		self.reset = Signal()
 		self.o = Signal(n_out)
 
 		###
@@ -17,12 +20,16 @@ def __init__(self, n_out, n_state=31, taps=[27, 30]):
 			curval.insert(0, nv)
 			curval.pop()
 
-		self.sync += If(self.ce,
+		self.sync += If(self.reset,
+				state.eq(0),
+				self.o.eq(0)
+			).Elif(self.ce,
 				state.eq(Cat(*curval[:n_state])),
 				self.o.eq(Cat(*curval))
 			)
 
 def _print_lfsr_code():
+	from migen.fhdl import verilog
 	dut = LFSR(3, 4, [3, 2])
 	print(verilog.convert(dut, ios={dut.ce, dut.o}))
 
@@ -40,6 +47,62 @@ def _sim_lfsr():
 	sim = Simulator(tb)
 	sim.run(20)
 
+memtest_magic = 0x361f
+
+class MemtestWriter(Module):
+	def __init__(self, lasmim):
+		self._r_magic = CSRStatus(16)
+		self._r_reset = CSR()
+		self.submodules._dma = DMAWriteController(dma_lasmi.Writer(lasmim), MODE_SINGLE_SHOT)
+
+		###
+
+		self.comb += self._r_magic.status.eq(memtest_magic)
+
+		lfsr = LFSR(lasmim.dw)
+		self.submodules += lfsr
+		self.comb += lfsr.reset.eq(self._r_reset.re)
+
+		self.comb += [
+			self._dma.data.stb.eq(1),
+			lfsr.ce.eq(self._dma.data.ack),
+			self._dma.data.payload.d.eq(lfsr.o)
+		]
+
+	def get_csrs(self):
+		return [self._r_magic, self._r_reset] + self._dma.get_csrs()
+
+class MemtestReader(Module):
+	def __init__(self, lasmim):
+		self._r_magic = CSRStatus(16)
+		self._r_reset = CSR()
+		self._r_error_count = CSRStatus(lasmim.aw)
+		self.submodules._dma = DMAReadController(dma_lasmi.Reader(lasmim), MODE_SINGLE_SHOT)
+
+		###
+
+		self.comb += self._r_magic.status.eq(memtest_magic)
+
+		lfsr = LFSR(lasmim.dw)
+		self.submodules += lfsr
+		self.comb += lfsr.reset.eq(self._r_reset.re)
+
+		self.comb += [
+			lfsr.ce.eq(self._dma.data.stb),
+			self._dma.data.ack.eq(1)
+		]
+		err_cnt = self._r_error_count.status
+		self.sync += [
+			If(self._r_reset.re,
+				err_cnt.eq(0)
+			).Elif(self._dma.data.stb,
+				If(self._dma.data.payload.d != lfsr.o, err_cnt.eq(err_cnt + 1))
+			)
+		]
+
+	def get_csrs(self):
+		return [self._r_magic, self._r_reset, self._r_error_count] + self._dma.get_csrs()
+
 if __name__ == "__main__":
 	_print_lfsr_code()
 	_sim_lfsr()
diff --git a/top.py b/top.py
@@ -10,7 +10,7 @@
 
 from milkymist import mxcrg, lm32, norflash, uart, s6ddrphy, dfii, lasmicon, \
 	identifier, timer, minimac3, framebuffer, dvisampler, \
-	counteradc, gpio
+	counteradc, gpio, memtest
 from milkymist.cif import get_macros
 
 version = get_macros("common/version.h")["VERSION"][1:-1]
@@ -89,7 +89,9 @@ class SoC(Module):
 		"dvisampler1_edid_mem":	11,
 		"pots":					12,
 		"buttons":				13,
-		"leds":					14
+		"leds":					14,
+		"memtest_w":			15,
+		"memtest_r":			16
 	}
 
 	interrupt_map = {
@@ -100,13 +102,18 @@ class SoC(Module):
 		"dvisampler1":	4,
 	}
 
-	def __init__(self, platform, platform_name):
+	def __init__(self, platform, platform_name, with_memtest):
 		#
 		# LASMI
 		#
 		self.submodules.lasmicon = lasmicon.LASMIcon(sdram_phy, sdram_geom, sdram_timing)
-		self.submodules.lasmixbar = lasmibus.Crossbar([self.lasmicon.lasmic], 5, self.lasmicon.nrowbits)
-		lasmim_wb, lasmim_fb0, lasmim_fb1, lasmim_dvi0, lasmim_dvi1 = self.lasmixbar.masters
+		n_lasmims = 7 if with_memtest else 5
+		self.submodules.lasmixbar = lasmibus.Crossbar([self.lasmicon.lasmic], n_lasmims, self.lasmicon.nrowbits)
+		lasmims = list(self.lasmixbar.masters)
+		lasmim_wb, lasmim_fb0, lasmim_fb1, lasmim_dvi0, lasmim_dvi1 = (lasmims.pop() for i in range(5))
+		if with_memtest:
+			lasmim_mtw, lasmim_mtr = lasmims.pop(), lasmims.pop()
+		assert(not lasmims)
 
 		#
 		# DFI
@@ -162,6 +169,9 @@ def __init__(self, platform, platform_name):
 				[pots_pads.blackout, pots_pads.crossfade])
 			self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
 			self.submodules.leds = gpio.GPIOOut(Cat(*[platform.request("user_led", i) for i in range(2)]))
+		if with_memtest:
+			self.submodules.memtest_w = memtest.MemtestWriter(lasmim_mtw)
+			self.submodules.memtest_r = memtest.MemtestReader(lasmim_mtr)
 
 		self.submodules.csrbankarray = csrgen.BankArray(self,
 			lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])