Generate all clocks for the DDR PHY

m-labs · Feb 16, 2012 · 72f9af9 · 72f9af9
1 parent 859c9d8
commit 72f9af9
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Showing 7 changed files with 495 additions and 100 deletions.
diff --git a/build.py b/build.py
@@ -10,7 +10,7 @@ def add_core_dir(d):
 def add_core_files(d, files):
 	for f in files:
 		verilog_sources.append(os.path.join("verilog", d, f))
-add_core_dir("m1reset")
+add_core_dir("m1crg")
 add_core_files("lm32", ["lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
 	"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
 	"lm32_shifter.v", "lm32_multiplier_spartan6.v", "lm32_mc_arithmetic.v",
@@ -59,4 +59,4 @@ def str2file(filename, contents):
 os.system("par -ol high -w soc.ncd soc-routed.ncd")
 
 # bitgen
-os.system("bitgen -g LCK_cycle:6 -g Binary:Yes -g INIT_9K:Yes -w soc-routed.ncd soc.bit")
+os.system("bitgen -g Binary:Yes -g INIT_9K:Yes -w soc-routed.ncd soc.bit")
diff --git a/constraints.py b/constraints.py
@@ -1,4 +1,4 @@
-def get(ns, clkfx_sys, reset0, norflash0, uart0):
+def get(ns, crg0, norflash0, uart0):
 	constraints = []
 	def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
 		constraints.append((ns.get_name(signal), vec, pin, iostandard, extra))
@@ -8,12 +8,12 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
 			add(signal, p, i, iostandard, extra)
 			i += 1
 
-	add(clkfx_sys.clkin, "AB11", extra="TNM_NET = \"GRPclk50\"")
-
-	add(reset0.trigger_reset, "AA4")
-	add(reset0.ac97_rst_n, "D6")
-	add(reset0.videoin_rst_n, "W17")
-	add(reset0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
+	add(crg0.clkin, "AB11", extra="TNM_NET = \"GRPclk50\"")
+	add(crg0.ac97_rst_n, "D6")
+	add(crg0.videoin_rst_n, "W17")
+	add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
+	add(crg0.rd_clk_lb, "K5")
+	add(crg0.trigger_reset, "AA4")
 
 	add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
 		"F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",

diff --git a/milkymist/m1crg/__init__.py b/milkymist/m1crg/__init__.py
@@ -0,0 +1,51 @@
+from fractions import Fraction
+
+from migen.fhdl.structure import *
+
+class M1CRG:
+	def __init__(self, infreq, outfreq1x):
+		self.clkin = Signal()
+		self.trigger_reset = Signal()
+
+		generated = []
+		for name in [
+			"sys_clk",
+			"sys_rst",
+			"ac97_rst_n",
+			"videoin_rst_n",
+			"flash_rst_n",
+			"clk2x_90",
+			"clk4x_wr_left",
+			"clk4x_wr_strb_left",
+			"clk4x_wr_right",
+			"clk4x_wr_strb_right",
+			"clk4x_rd_left",
+			"clk4x_rd_strb_left",
+			"clk4x_rd_right",
+			"clk4x_rd_strb_right"
+		  ]:
+			s = Signal(name=name)
+			setattr(self, name, s)
+			generated.append((name, s))  
+
+		self.rd_clk_lb = Signal()
+
+		ratio = Fraction(outfreq1x)/Fraction(infreq)
+		in_period = float(Fraction(1000000000)/Fraction(infreq))
+
+		self._inst = Instance("m1crg",
+			generated,
+			[
+				("clkin", self.clkin),
+				("trigger_reset", self.trigger_reset),
+				("rd_clk_lb", self.rd_clk_lb) # TODO: inout
+			], [
+				("in_period", in_period),
+				("f_mult", ratio.numerator),
+				("f_div", ratio.denominator)
+			]
+		)
+
+	def get_fragment(self):
+		return Fragment(instances=[self._inst],
+			pads={self.clkin, self.ac97_rst_n, self.videoin_rst_n, self.flash_rst_n, self.rd_clk_lb})
diff --git a/milkymist/m1reset/__init__.py b/milkymist/m1reset/__init__.py
diff --git a/top.py b/top.py
@@ -1,20 +1,23 @@
+from fractions import Fraction
+
 from migen.fhdl.structure import *
 from migen.fhdl import verilog, autofragment
 from migen.bus import wishbone, asmibus, wishbone2asmi, csr, wishbone2csr
 
-from milkymist import m1reset, clkfx, lm32, norflash, uart, sram
+from milkymist import m1crg, lm32, norflash, uart, sram#, s6ddrphy
 import constraints
 
 MHz = 1000000
-clk_freq = 80*MHz
+clk_freq = (83 + Fraction(1, 3))*MHz
 sram_size = 4096 # in bytes
 l2_size = 8192 # in bytes
 
 def get():
 	#
 	# ASMI
 	#
-	asmihub0 = asmibus.Hub(24, 64, 8) # TODO: get hub from memory controller
+	#ddrphy0 = s6ddrphy.S6DDRPHY(13, 2, 128)
+	asmihub0 = asmibus.Hub(23, 128, 12) # TODO: get hub from memory controller
 	asmiport_wb = asmihub0.get_port()
 	asmihub0.finalize()
 
@@ -62,15 +65,14 @@ def get():
 	#
 	# Housekeeping
 	#
-	clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
-	reset0 = m1reset.M1Reset()
+	crg0 = m1crg.M1CRG(50*MHz, clk_freq)
 
 	frag = autofragment.from_local() + interrupts
 	src_verilog, vns = verilog.convert(frag,
-		{clkfx_sys.clkin, reset0.trigger_reset},
+		{crg0.trigger_reset},
 		name="soc",
-		clk_signal=clkfx_sys.clkout,
-		rst_signal=reset0.sys_rst,
+		clk_signal=crg0.sys_clk,
+		rst_signal=crg0.sys_rst,
 		return_ns=True)
-	src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
+	src_ucf = constraints.get(vns, crg0, norflash0, uart0)
 	return (src_verilog, src_ucf)