Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/migen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 80970b203c43
Choose a base ref
...
head repository: m-labs/migen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 3c75121783e5
Choose a head ref
  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Mar 11, 2013

  1. README: update

    Sebastien Bourdeauducq committed Mar 11, 2013
    Copy the full SHA
    c4d9734 View commit details
  2. fhdl/tracer: remove leading underscores from names

    Sebastien Bourdeauducq committed Mar 11, 2013
    Copy the full SHA
    3c75121 View commit details
Showing with 36 additions and 10 deletions.
  1. +28 −10 README
  2. +8 −0 migen/fhdl/tracer.py
38 changes: 28 additions & 10 deletions README
Original file line number Diff line number Diff line change
@@ -1,25 +1,43 @@
Migen (Milkymist Generator)
a Python toolbox for building complex digital hardware

Migen aims at automating further the VLSI design process. Migen makes it
possible to apply modern software concepts such as object-oriented
programming and metaprogramming to design hardware. This results in more
elegant and easily maintained designs and reduces the incidence of human
errors. Built on these principles, it also provides tools to build
synchronous designs more productively, integrate system-on-chips, design
dataflow systems, and more. Migen will become the foundation for the
next-generation Milkymist SoC.
Despite being faster than schematics entry, hardware design with Verilog and
VHDL remains tedious and inefficient for several reasons. The event-driven
model introduces issues and manual coding that are unnecessary for synchronous
circuits, which represent the lion's share of today's logic designs. Counter-
intuitive arithmetic rules result in steeper learning curves and provide a
fertile ground for subtle bugs in designs. Finally, support for procedural
generation of logic (metaprogramming) through "generate" statements is very
limited and restricts the ways code can be made generic, reused and organized.

To address those issues, we have developed the Migen FHDL library that
replaces the event-driven paradigm with the notions of combinatorial and
synchronous statements, has arithmetic rules that make integers always behave
like mathematical integers, and most importantly allows the design's logic to
be constructed by a Python program. This last point enables hardware designers
to take advantage of the richness of the Python language - object oriented
programming, function parameters, generators, operator overloading, libraries,
etc. - to build well organized, reusable and elegant designs.

Other Migen libraries are built on FHDL and provide various tools such as a
system-on-chip interconnect infrastructure, a dataflow programming system, a
more traditional high-level synthesizer that compiles Python routines into
state machines with datapaths, and a simulator that allows test benches to be
written in Python.

Migen is the foundation of the next-generation Milkymist SoC.

See the doc/ folder for a more complete description.

Code repository:
https://github.com/milkymist/migen
Experimental version of the Milkymist SoC based on Migen:
New Milkymist SoC based on Migen:
https://github.com/milkymist/milkymist-ng

Migen is designed for Python 3.2.
Migen is designed for Python 3.

Send questions, comments and patches to devel [AT] lists.milkymist.org
There is a lot of room for improvement in many areas, contributions welcome.
We are also on IRC: #milkymist on the Freenode network.

See LICENSE file for copyright and license info.
8 changes: 8 additions & 0 deletions migen/fhdl/tracer.py
Original file line number Diff line number Diff line change
@@ -28,6 +28,11 @@ def get_var_name(frame):
else:
return None

def remove_underscore(s):
if len(s) > 2 and s[0] == "_" and s[1] != "_":
s = s[1:]
return s

name_to_idx = defaultdict(int)
classname_to_objs = dict()

@@ -44,6 +49,7 @@ def trace_back(varname=None):
if varname is None:
varname = get_var_name(frame)
if varname is not None:
varname = remove_underscore(varname)
l.insert(0, (varname, name_to_idx[varname]))
name_to_idx[varname] += 1

@@ -61,6 +67,7 @@ def trace_back(varname=None):
modules = frame.f_globals["__name__"]
modules = modules.split(".")
coname = modules[len(modules)-1]
coname = remove_underscore(coname)
l.insert(0, (coname, name_to_idx[coname]))
name_to_idx[coname] += 1
else:
@@ -76,6 +83,7 @@ def trace_back(varname=None):
except ValueError:
idx = len(objs)
objs.append(obj)
classname = remove_underscore(classname)
l.insert(0, (classname, idx))

varname = None