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Use new bitwidth/signedness system
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Sebastien Bourdeauducq committed Nov 29, 2012
1 parent 7e2bc00 commit 8bf6945
Showing 10 changed files with 76 additions and 76 deletions.
2 changes: 1 addition & 1 deletion constraints.py
Original file line number Diff line number Diff line change
@@ -4,7 +4,7 @@ def __init__(self, crg0, norflash0, uart0, ddrphy0, minimac0, fb0):
def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
self.constraints.append((signal, vec, pin, iostandard, extra))
def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
assert(signal.bv.width == len(pins))
assert(signal.nbits == len(pins))
i = 0
for p in pins:
add(signal, p, i, iostandard, extra)
16 changes: 8 additions & 8 deletions milkymist/asmicon/bankmachine.py
Original file line number Diff line number Diff line change
@@ -42,8 +42,8 @@ def __init__(self, slicer, bankn, slots):
self.nslots = len(self.slots)
self.stb = Signal()
self.ack = Signal()
self.tag = Signal(BV(bits_for(self.nslots-1)))
self.adr = Signal(self.slots[0].adr.bv)
self.tag = Signal(bits_for(self.nslots-1))
self.adr = Signal(self.slots[0].adr.nbits)
self.we = Signal()

# derived classes should drive rr.request
@@ -54,7 +54,7 @@ def get_fragment(self):
rr = self.rr

# Multiplex
state = Signal(BV(2))
state = Signal(2)
comb += [
state.eq(Array(slot.state for slot in self.slots)[rr.grant]),
self.adr.eq(Array(slot.adr for slot in self.slots)[rr.grant]),
@@ -98,9 +98,9 @@ def get_fragment(self):
outstandings.append(outstanding)

# Row tracking
openrow_r = Signal(BV(self.slicer.geom_settings.row_a))
openrow_n = Signal(BV(self.slicer.geom_settings.row_a))
openrow = Signal(BV(self.slicer.geom_settings.row_a))
openrow_r = Signal(self.slicer.geom_settings.row_a)
openrow_n = Signal(self.slicer.geom_settings.row_a)
openrow = Signal(self.slicer.geom_settings.row_a)
comb += [
openrow_n.eq(self.slicer.row(self.adr)),
If(self.stb,
@@ -207,7 +207,7 @@ def get_fragment(self):

# Row tracking
has_openrow = Signal()
openrow = Signal(BV(self.geom_settings.row_a))
openrow = Signal(self.geom_settings.row_a)
hit = Signal()
comb.append(hit.eq(openrow == slicer.row(cmdsource.adr)))
track_open = Signal()
@@ -238,7 +238,7 @@ def get_fragment(self):
# Respect write-to-precharge specification
precharge_ok = Signal()
t_unsafe_precharge = 2 + self.timing_settings.tWR - 1
unsafe_precharge_count = Signal(BV(bits_for(t_unsafe_precharge)))
unsafe_precharge_count = Signal(bits_for(t_unsafe_precharge))
comb.append(precharge_ok.eq(unsafe_precharge_count == 0))
sync += [
If(self.cmd.stb & self.cmd.ack & self.cmd.is_write,
16 changes: 8 additions & 8 deletions milkymist/asmicon/multiplexer.py
Original file line number Diff line number Diff line change
@@ -5,8 +5,8 @@

class CommandRequest:
def __init__(self, a, ba):
self.a = Signal(BV(a))
self.ba = Signal(BV(ba))
self.a = Signal(a)
self.ba = Signal(ba)
self.cas_n = Signal(reset=1)
self.ras_n = Signal(reset=1)
self.we_n = Signal(reset=1)
@@ -18,7 +18,7 @@ def __init__(self, a, ba, tagbits):
self.ack = Signal()
self.is_read = Signal()
self.is_write = Signal()
self.tag = Signal(BV(tagbits))
self.tag = Signal(tagbits)

class _CommandChooser:
def __init__(self, requests, tagbits):
@@ -64,7 +64,7 @@ def __init__(self, commands, dfi):

ncmd = len(self.commands)
nph = len(self.dfi.phases)
self.sel = [Signal(BV(bits_for(ncmd-1))) for i in range(nph)]
self.sel = [Signal(bits_for(ncmd-1)) for i in range(nph)]

def get_fragment(self):
comb = []
@@ -103,9 +103,9 @@ def get_fragment(self):
tagbits = len(self.hub.tag_call)

rd_valid = Signal()
rd_tag = Signal(BV(tagbits))
rd_tag = Signal(tagbits)
wr_valid = Signal()
wr_tag = Signal(BV(tagbits))
wr_tag = Signal(tagbits)
comb += [
self.hub.call.eq(rd_valid | wr_valid),
If(wr_valid,
@@ -117,7 +117,7 @@ def get_fragment(self):

rd_delay = self.timing_settings.rd_delay + 1
rd_valid_d = [Signal() for i in range(rd_delay)]
rd_tag_d = [Signal(BV(tagbits)) for i in range(rd_delay)]
rd_tag_d = [Signal(tagbits) for i in range(rd_delay)]
for i in range(rd_delay):
if i:
sync += [
@@ -194,7 +194,7 @@ def anti_starvation(timeout):
max_time = Signal()
if timeout:
t = timeout - 1
time = Signal(BV(bits_for(t)))
time = Signal(bits_for(t))
comb.append(max_time.eq(time == 0))
sync.append(
If(~en,
2 changes: 1 addition & 1 deletion milkymist/asmicon/refresher.py
Original file line number Diff line number Diff line change
@@ -45,7 +45,7 @@ def get_fragment(self):
])

# Periodic refresh counter
counter = Signal(BV(bits_for(self.tREFI - 1)))
counter = Signal(bits_for(self.tREFI - 1))
start = Signal()
sync += [
start.eq(0),
78 changes: 39 additions & 39 deletions milkymist/framebuffer/__init__.py
Original file line number Diff line number Diff line change
@@ -12,51 +12,51 @@
_bpp = 32
_bpc = 10
_pixel_layout = [
("b", BV(_bpc)),
("g", BV(_bpc)),
("r", BV(_bpc)),
("pad", BV(_bpp-3*_bpc))
("b", _bpc),
("g", _bpc),
("r", _bpc),
("pad", _bpp-3*_bpc)
]

_bpc_dac = 8
_dac_layout = [
("hsync", BV(1)),
("vsync", BV(1)),
("b", BV(_bpc_dac)),
("g", BV(_bpc_dac)),
("r", BV(_bpc_dac))
("hsync", 1),
("vsync", 1),
("b", _bpc_dac),
("g", _bpc_dac),
("r", _bpc_dac)
]

class _FrameInitiator(spi.SingleGenerator):
def __init__(self, asmi_bits, length_bits, alignment_bits):
layout = [
("hres", BV(_hbits), 640),
("hsync_start", BV(_hbits), 656),
("hsync_end", BV(_hbits), 752),
("hscan", BV(_hbits), 799),
("hres", _hbits, 640),
("hsync_start", _hbits, 656),
("hsync_end", _hbits, 752),
("hscan", _hbits, 799),

("vres", BV(_vbits), 480),
("vsync_start", BV(_vbits), 492),
("vsync_end", BV(_vbits), 494),
("vscan", BV(_vbits), 524),
("vres", _vbits, 480),
("vsync_start", _vbits, 492),
("vsync_end", _vbits, 494),
("vscan", _vbits, 524),

("base", BV(asmi_bits), 0, alignment_bits),
("length", BV(length_bits), 640*480*4, alignment_bits)
("base", asmi_bits, 0, alignment_bits),
("length", length_bits, 640*480*4, alignment_bits)
]
super().__init__(layout, spi.MODE_CONTINUOUS)

class VTG(Actor):
def __init__(self):
super().__init__(
("timing", Sink, [
("hres", BV(_hbits)),
("hsync_start", BV(_hbits)),
("hsync_end", BV(_hbits)),
("hscan", BV(_hbits)),
("vres", BV(_vbits)),
("vsync_start", BV(_vbits)),
("vsync_end", BV(_vbits)),
("vscan", BV(_vbits))]),
("hres", _hbits),
("hsync_start", _hbits),
("hsync_end", _hbits),
("hscan", _hbits),
("vres", _vbits),
("vsync_start", _vbits),
("vsync_end", _vbits),
("vscan", _vbits)]),
("pixels", Sink, _pixel_layout),
("dac", Source, _dac_layout)
)
@@ -67,8 +67,8 @@ def get_fragment(self):
active = Signal()

generate_en = Signal()
hcounter = Signal(BV(_hbits))
vcounter = Signal(BV(_vbits))
hcounter = Signal(_hbits)
vcounter = Signal(_vbits)

skip = _bpc - _bpc_dac
comb = [
@@ -118,27 +118,27 @@ def __init__(self):

self.vga_hsync_n = Signal()
self.vga_vsync_n = Signal()
self.vga_r = Signal(BV(_bpc_dac))
self.vga_g = Signal(BV(_bpc_dac))
self.vga_b = Signal(BV(_bpc_dac))
self.vga_r = Signal(_bpc_dac)
self.vga_g = Signal(_bpc_dac)
self.vga_b = Signal(_bpc_dac)

def get_fragment(self):
data_width = 2+3*_bpc_dac
asfifo = Instance("asfifo",
Instance.Parameter("data_width", data_width),
Instance.Parameter("address_width", 8),

Instance.Output("data_out", BV(data_width)),
Instance.Output("empty", BV(1)),
Instance.Input("read_en", BV(1)),
Instance.Output("data_out", data_width),
Instance.Output("empty", 1),
Instance.Input("read_en", 1),
Instance.ClockPort("clk_read", "vga"),

Instance.Input("data_in", BV(data_width)),
Instance.Output("full", BV(1)),
Instance.Input("write_en", BV(1)),
Instance.Input("data_in", data_width),
Instance.Output("full", 1),
Instance.Input("write_en", 1),
Instance.ClockPort("clk_write"),

Instance.Input("rst", BV(1)))
Instance.Input("rst", 1))
t = self.token("dac")
return Fragment(
[
14 changes: 7 additions & 7 deletions milkymist/lm32/__init__.py
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@ class LM32:
def __init__(self):
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(BV(32))
self.interrupt = Signal(32)
self.ext_break = Signal()
self._inst = Instance("lm32_top",
Instance.ClockPort("clk_i"),
@@ -14,33 +14,33 @@ def __init__(self):
Instance.Input("interrupt", self.interrupt),
#Instance.Input("ext_break", self.ext_break),

Instance.Output("I_ADR_O", BV(32)),
Instance.Output("I_ADR_O", 32),
Instance.Output("I_DAT_O", i.dat_w),
Instance.Output("I_SEL_O", i.sel),
Instance.Output("I_CYC_O", i.cyc),
Instance.Output("I_STB_O", i.stb),
Instance.Output("I_WE_O", i.we),
Instance.Output("I_CTI_O", i.cti),
Instance.Output("I_LOCK_O", BV(1)),
Instance.Output("I_LOCK_O", 1),
Instance.Output("I_BTE_O", i.bte),
Instance.Input("I_DAT_I", i.dat_r),
Instance.Input("I_ACK_I", i.ack),
Instance.Input("I_ERR_I", i.err),
Instance.Input("I_RTY_I", BV(1)),
Instance.Input("I_RTY_I", 1),

Instance.Output("D_ADR_O", BV(32)),
Instance.Output("D_ADR_O", 32),
Instance.Output("D_DAT_O", d.dat_w),
Instance.Output("D_SEL_O", d.sel),
Instance.Output("D_CYC_O", d.cyc),
Instance.Output("D_STB_O", d.stb),
Instance.Output("D_WE_O", d.we),
Instance.Output("D_CTI_O", d.cti),
Instance.Output("D_LOCK_O", BV(1)),
Instance.Output("D_LOCK_O", 1),
Instance.Output("D_BTE_O", d.bte),
Instance.Input("D_DAT_I", d.dat_r),
Instance.Input("D_ACK_I", d.ack),
Instance.Input("D_ERR_I", d.err),
Instance.Input("D_RTY_I", BV(1)))
Instance.Input("D_RTY_I", 1))

def get_fragment(self):
comb = [
4 changes: 2 additions & 2 deletions milkymist/minimac3/__init__.py
Original file line number Diff line number Diff line change
@@ -10,11 +10,11 @@ class MiniMAC:
def __init__(self, address):
# PHY signals
self.phy_tx_clk = Signal()
self.phy_tx_data = Signal(BV(4))
self.phy_tx_data = Signal(4)
self.phy_tx_en = Signal()
self.phy_tx_er = Signal()
self.phy_rx_clk = Signal()
self.phy_rx_data = Signal(BV(4))
self.phy_rx_data = Signal(4)
self.phy_dv = Signal()
self.phy_rx_er = Signal()
self.phy_col = Signal()
4 changes: 2 additions & 2 deletions milkymist/norflash/__init__.py
Original file line number Diff line number Diff line change
@@ -8,8 +8,8 @@ def __init__(self, adr_width, rd_timing):
self.rd_timing = rd_timing

self.bus = wishbone.Interface()
self.adr = Signal(BV(adr_width-1))
self.d = Signal(BV(16))
self.adr = Signal(adr_width-1)
self.d = Signal(16)
self.oe_n = Signal()
self.we_n = Signal()
self.ce_n = Signal()
2 changes: 1 addition & 1 deletion milkymist/s6ddrphy/__init__.py
Original file line number Diff line number Diff line change
@@ -30,7 +30,7 @@ def __init__(self, a, ba, d):
("sd_dqs", d//16, Instance.InOut)

]:
s = Signal(BV(width), name=name)
s = Signal(width, name=name)
setattr(self, name, s)
inst_items.append(cl(name, s))

14 changes: 7 additions & 7 deletions milkymist/uart/__init__.py
Original file line number Diff line number Diff line change
@@ -19,7 +19,7 @@ def __init__(self, address, clk_freq, baud=115200):

def get_fragment(self):
enable16 = Signal()
enable16_counter = Signal(BV(16))
enable16_counter = Signal(16)
comb = [
enable16.eq(enable16_counter == 0)
]
@@ -30,9 +30,9 @@ def get_fragment(self):
]

# TX
tx_reg = Signal(BV(8))
tx_bitcount = Signal(BV(4))
tx_count16 = Signal(BV(4))
tx_reg = Signal(8)
tx_bitcount = Signal(4)
tx_count16 = Signal(4)
tx_busy = self._tx_event.trigger
sync += [
If(self._rxtx.re,
@@ -66,9 +66,9 @@ def get_fragment(self):
rx.eq(rx0)
]
rx_r = Signal()
rx_reg = Signal(BV(8))
rx_bitcount = Signal(BV(4))
rx_count16 = Signal(BV(4))
rx_reg = Signal(8)
rx_bitcount = Signal(4)
rx_count16 = Signal(4)
rx_busy = Signal()
rx_done = self._rx_event.trigger
rx_data = self._rxtx.w

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