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Commit 8bf6945

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author
Sebastien Bourdeauducq
committedNov 29, 2012
Use new bitwidth/signedness system
·
0.120.1
1 parent 7e2bc00 commit 8bf6945

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10 files changed

+76
-76
lines changed

10 files changed

+76
-76
lines changed
 

Diff for: ‎constraints.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ def __init__(self, crg0, norflash0, uart0, ddrphy0, minimac0, fb0):
44
def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
55
self.constraints.append((signal, vec, pin, iostandard, extra))
66
def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
7-
assert(signal.bv.width == len(pins))
7+
assert(signal.nbits == len(pins))
88
i = 0
99
for p in pins:
1010
add(signal, p, i, iostandard, extra)

Diff for: ‎milkymist/asmicon/bankmachine.py

+8-8
Original file line numberDiff line numberDiff line change
@@ -42,8 +42,8 @@ def __init__(self, slicer, bankn, slots):
4242
self.nslots = len(self.slots)
4343
self.stb = Signal()
4444
self.ack = Signal()
45-
self.tag = Signal(BV(bits_for(self.nslots-1)))
46-
self.adr = Signal(self.slots[0].adr.bv)
45+
self.tag = Signal(bits_for(self.nslots-1))
46+
self.adr = Signal(self.slots[0].adr.nbits)
4747
self.we = Signal()
4848

4949
# derived classes should drive rr.request
@@ -54,7 +54,7 @@ def get_fragment(self):
5454
rr = self.rr
5555

5656
# Multiplex
57-
state = Signal(BV(2))
57+
state = Signal(2)
5858
comb += [
5959
state.eq(Array(slot.state for slot in self.slots)[rr.grant]),
6060
self.adr.eq(Array(slot.adr for slot in self.slots)[rr.grant]),
@@ -98,9 +98,9 @@ def get_fragment(self):
9898
outstandings.append(outstanding)
9999

100100
# Row tracking
101-
openrow_r = Signal(BV(self.slicer.geom_settings.row_a))
102-
openrow_n = Signal(BV(self.slicer.geom_settings.row_a))
103-
openrow = Signal(BV(self.slicer.geom_settings.row_a))
101+
openrow_r = Signal(self.slicer.geom_settings.row_a)
102+
openrow_n = Signal(self.slicer.geom_settings.row_a)
103+
openrow = Signal(self.slicer.geom_settings.row_a)
104104
comb += [
105105
openrow_n.eq(self.slicer.row(self.adr)),
106106
If(self.stb,
@@ -207,7 +207,7 @@ def get_fragment(self):
207207

208208
# Row tracking
209209
has_openrow = Signal()
210-
openrow = Signal(BV(self.geom_settings.row_a))
210+
openrow = Signal(self.geom_settings.row_a)
211211
hit = Signal()
212212
comb.append(hit.eq(openrow == slicer.row(cmdsource.adr)))
213213
track_open = Signal()
@@ -238,7 +238,7 @@ def get_fragment(self):
238238
# Respect write-to-precharge specification
239239
precharge_ok = Signal()
240240
t_unsafe_precharge = 2 + self.timing_settings.tWR - 1
241-
unsafe_precharge_count = Signal(BV(bits_for(t_unsafe_precharge)))
241+
unsafe_precharge_count = Signal(bits_for(t_unsafe_precharge))
242242
comb.append(precharge_ok.eq(unsafe_precharge_count == 0))
243243
sync += [
244244
If(self.cmd.stb & self.cmd.ack & self.cmd.is_write,

Diff for: ‎milkymist/asmicon/multiplexer.py

+8-8
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55

66
class CommandRequest:
77
def __init__(self, a, ba):
8-
self.a = Signal(BV(a))
9-
self.ba = Signal(BV(ba))
8+
self.a = Signal(a)
9+
self.ba = Signal(ba)
1010
self.cas_n = Signal(reset=1)
1111
self.ras_n = Signal(reset=1)
1212
self.we_n = Signal(reset=1)
@@ -18,7 +18,7 @@ def __init__(self, a, ba, tagbits):
1818
self.ack = Signal()
1919
self.is_read = Signal()
2020
self.is_write = Signal()
21-
self.tag = Signal(BV(tagbits))
21+
self.tag = Signal(tagbits)
2222

2323
class _CommandChooser:
2424
def __init__(self, requests, tagbits):
@@ -64,7 +64,7 @@ def __init__(self, commands, dfi):
6464

6565
ncmd = len(self.commands)
6666
nph = len(self.dfi.phases)
67-
self.sel = [Signal(BV(bits_for(ncmd-1))) for i in range(nph)]
67+
self.sel = [Signal(bits_for(ncmd-1)) for i in range(nph)]
6868

6969
def get_fragment(self):
7070
comb = []
@@ -103,9 +103,9 @@ def get_fragment(self):
103103
tagbits = len(self.hub.tag_call)
104104

105105
rd_valid = Signal()
106-
rd_tag = Signal(BV(tagbits))
106+
rd_tag = Signal(tagbits)
107107
wr_valid = Signal()
108-
wr_tag = Signal(BV(tagbits))
108+
wr_tag = Signal(tagbits)
109109
comb += [
110110
self.hub.call.eq(rd_valid | wr_valid),
111111
If(wr_valid,
@@ -117,7 +117,7 @@ def get_fragment(self):
117117

118118
rd_delay = self.timing_settings.rd_delay + 1
119119
rd_valid_d = [Signal() for i in range(rd_delay)]
120-
rd_tag_d = [Signal(BV(tagbits)) for i in range(rd_delay)]
120+
rd_tag_d = [Signal(tagbits) for i in range(rd_delay)]
121121
for i in range(rd_delay):
122122
if i:
123123
sync += [
@@ -194,7 +194,7 @@ def anti_starvation(timeout):
194194
max_time = Signal()
195195
if timeout:
196196
t = timeout - 1
197-
time = Signal(BV(bits_for(t)))
197+
time = Signal(bits_for(t))
198198
comb.append(max_time.eq(time == 0))
199199
sync.append(
200200
If(~en,

Diff for: ‎milkymist/asmicon/refresher.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ def get_fragment(self):
4545
])
4646

4747
# Periodic refresh counter
48-
counter = Signal(BV(bits_for(self.tREFI - 1)))
48+
counter = Signal(bits_for(self.tREFI - 1))
4949
start = Signal()
5050
sync += [
5151
start.eq(0),

Diff for: ‎milkymist/framebuffer/__init__.py

+39-39
Original file line numberDiff line numberDiff line change
@@ -12,51 +12,51 @@
1212
_bpp = 32
1313
_bpc = 10
1414
_pixel_layout = [
15-
("b", BV(_bpc)),
16-
("g", BV(_bpc)),
17-
("r", BV(_bpc)),
18-
("pad", BV(_bpp-3*_bpc))
15+
("b", _bpc),
16+
("g", _bpc),
17+
("r", _bpc),
18+
("pad", _bpp-3*_bpc)
1919
]
2020

2121
_bpc_dac = 8
2222
_dac_layout = [
23-
("hsync", BV(1)),
24-
("vsync", BV(1)),
25-
("b", BV(_bpc_dac)),
26-
("g", BV(_bpc_dac)),
27-
("r", BV(_bpc_dac))
23+
("hsync", 1),
24+
("vsync", 1),
25+
("b", _bpc_dac),
26+
("g", _bpc_dac),
27+
("r", _bpc_dac)
2828
]
2929

3030
class _FrameInitiator(spi.SingleGenerator):
3131
def __init__(self, asmi_bits, length_bits, alignment_bits):
3232
layout = [
33-
("hres", BV(_hbits), 640),
34-
("hsync_start", BV(_hbits), 656),
35-
("hsync_end", BV(_hbits), 752),
36-
("hscan", BV(_hbits), 799),
33+
("hres", _hbits, 640),
34+
("hsync_start", _hbits, 656),
35+
("hsync_end", _hbits, 752),
36+
("hscan", _hbits, 799),
3737

38-
("vres", BV(_vbits), 480),
39-
("vsync_start", BV(_vbits), 492),
40-
("vsync_end", BV(_vbits), 494),
41-
("vscan", BV(_vbits), 524),
38+
("vres", _vbits, 480),
39+
("vsync_start", _vbits, 492),
40+
("vsync_end", _vbits, 494),
41+
("vscan", _vbits, 524),
4242

43-
("base", BV(asmi_bits), 0, alignment_bits),
44-
("length", BV(length_bits), 640*480*4, alignment_bits)
43+
("base", asmi_bits, 0, alignment_bits),
44+
("length", length_bits, 640*480*4, alignment_bits)
4545
]
4646
super().__init__(layout, spi.MODE_CONTINUOUS)
4747

4848
class VTG(Actor):
4949
def __init__(self):
5050
super().__init__(
5151
("timing", Sink, [
52-
("hres", BV(_hbits)),
53-
("hsync_start", BV(_hbits)),
54-
("hsync_end", BV(_hbits)),
55-
("hscan", BV(_hbits)),
56-
("vres", BV(_vbits)),
57-
("vsync_start", BV(_vbits)),
58-
("vsync_end", BV(_vbits)),
59-
("vscan", BV(_vbits))]),
52+
("hres", _hbits),
53+
("hsync_start", _hbits),
54+
("hsync_end", _hbits),
55+
("hscan", _hbits),
56+
("vres", _vbits),
57+
("vsync_start", _vbits),
58+
("vsync_end", _vbits),
59+
("vscan", _vbits)]),
6060
("pixels", Sink, _pixel_layout),
6161
("dac", Source, _dac_layout)
6262
)
@@ -67,8 +67,8 @@ def get_fragment(self):
6767
active = Signal()
6868

6969
generate_en = Signal()
70-
hcounter = Signal(BV(_hbits))
71-
vcounter = Signal(BV(_vbits))
70+
hcounter = Signal(_hbits)
71+
vcounter = Signal(_vbits)
7272

7373
skip = _bpc - _bpc_dac
7474
comb = [
@@ -118,27 +118,27 @@ def __init__(self):
118118

119119
self.vga_hsync_n = Signal()
120120
self.vga_vsync_n = Signal()
121-
self.vga_r = Signal(BV(_bpc_dac))
122-
self.vga_g = Signal(BV(_bpc_dac))
123-
self.vga_b = Signal(BV(_bpc_dac))
121+
self.vga_r = Signal(_bpc_dac)
122+
self.vga_g = Signal(_bpc_dac)
123+
self.vga_b = Signal(_bpc_dac)
124124

125125
def get_fragment(self):
126126
data_width = 2+3*_bpc_dac
127127
asfifo = Instance("asfifo",
128128
Instance.Parameter("data_width", data_width),
129129
Instance.Parameter("address_width", 8),
130130

131-
Instance.Output("data_out", BV(data_width)),
132-
Instance.Output("empty", BV(1)),
133-
Instance.Input("read_en", BV(1)),
131+
Instance.Output("data_out", data_width),
132+
Instance.Output("empty", 1),
133+
Instance.Input("read_en", 1),
134134
Instance.ClockPort("clk_read", "vga"),
135135

136-
Instance.Input("data_in", BV(data_width)),
137-
Instance.Output("full", BV(1)),
138-
Instance.Input("write_en", BV(1)),
136+
Instance.Input("data_in", data_width),
137+
Instance.Output("full", 1),
138+
Instance.Input("write_en", 1),
139139
Instance.ClockPort("clk_write"),
140140

141-
Instance.Input("rst", BV(1)))
141+
Instance.Input("rst", 1))
142142
t = self.token("dac")
143143
return Fragment(
144144
[

Diff for: ‎milkymist/lm32/__init__.py

+7-7
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ class LM32:
55
def __init__(self):
66
self.ibus = i = wishbone.Interface()
77
self.dbus = d = wishbone.Interface()
8-
self.interrupt = Signal(BV(32))
8+
self.interrupt = Signal(32)
99
self.ext_break = Signal()
1010
self._inst = Instance("lm32_top",
1111
Instance.ClockPort("clk_i"),
@@ -14,33 +14,33 @@ def __init__(self):
1414
Instance.Input("interrupt", self.interrupt),
1515
#Instance.Input("ext_break", self.ext_break),
1616

17-
Instance.Output("I_ADR_O", BV(32)),
17+
Instance.Output("I_ADR_O", 32),
1818
Instance.Output("I_DAT_O", i.dat_w),
1919
Instance.Output("I_SEL_O", i.sel),
2020
Instance.Output("I_CYC_O", i.cyc),
2121
Instance.Output("I_STB_O", i.stb),
2222
Instance.Output("I_WE_O", i.we),
2323
Instance.Output("I_CTI_O", i.cti),
24-
Instance.Output("I_LOCK_O", BV(1)),
24+
Instance.Output("I_LOCK_O", 1),
2525
Instance.Output("I_BTE_O", i.bte),
2626
Instance.Input("I_DAT_I", i.dat_r),
2727
Instance.Input("I_ACK_I", i.ack),
2828
Instance.Input("I_ERR_I", i.err),
29-
Instance.Input("I_RTY_I", BV(1)),
29+
Instance.Input("I_RTY_I", 1),
3030

31-
Instance.Output("D_ADR_O", BV(32)),
31+
Instance.Output("D_ADR_O", 32),
3232
Instance.Output("D_DAT_O", d.dat_w),
3333
Instance.Output("D_SEL_O", d.sel),
3434
Instance.Output("D_CYC_O", d.cyc),
3535
Instance.Output("D_STB_O", d.stb),
3636
Instance.Output("D_WE_O", d.we),
3737
Instance.Output("D_CTI_O", d.cti),
38-
Instance.Output("D_LOCK_O", BV(1)),
38+
Instance.Output("D_LOCK_O", 1),
3939
Instance.Output("D_BTE_O", d.bte),
4040
Instance.Input("D_DAT_I", d.dat_r),
4141
Instance.Input("D_ACK_I", d.ack),
4242
Instance.Input("D_ERR_I", d.err),
43-
Instance.Input("D_RTY_I", BV(1)))
43+
Instance.Input("D_RTY_I", 1))
4444

4545
def get_fragment(self):
4646
comb = [

Diff for: ‎milkymist/minimac3/__init__.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -10,11 +10,11 @@ class MiniMAC:
1010
def __init__(self, address):
1111
# PHY signals
1212
self.phy_tx_clk = Signal()
13-
self.phy_tx_data = Signal(BV(4))
13+
self.phy_tx_data = Signal(4)
1414
self.phy_tx_en = Signal()
1515
self.phy_tx_er = Signal()
1616
self.phy_rx_clk = Signal()
17-
self.phy_rx_data = Signal(BV(4))
17+
self.phy_rx_data = Signal(4)
1818
self.phy_dv = Signal()
1919
self.phy_rx_er = Signal()
2020
self.phy_col = Signal()

Diff for: ‎milkymist/norflash/__init__.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@ def __init__(self, adr_width, rd_timing):
88
self.rd_timing = rd_timing
99

1010
self.bus = wishbone.Interface()
11-
self.adr = Signal(BV(adr_width-1))
12-
self.d = Signal(BV(16))
11+
self.adr = Signal(adr_width-1)
12+
self.d = Signal(16)
1313
self.oe_n = Signal()
1414
self.we_n = Signal()
1515
self.ce_n = Signal()

Diff for: ‎milkymist/s6ddrphy/__init__.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ def __init__(self, a, ba, d):
3030
("sd_dqs", d//16, Instance.InOut)
3131

3232
]:
33-
s = Signal(BV(width), name=name)
33+
s = Signal(width, name=name)
3434
setattr(self, name, s)
3535
inst_items.append(cl(name, s))
3636

Diff for: ‎milkymist/uart/__init__.py

+7-7
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ def __init__(self, address, clk_freq, baud=115200):
1919

2020
def get_fragment(self):
2121
enable16 = Signal()
22-
enable16_counter = Signal(BV(16))
22+
enable16_counter = Signal(16)
2323
comb = [
2424
enable16.eq(enable16_counter == 0)
2525
]
@@ -30,9 +30,9 @@ def get_fragment(self):
3030
]
3131

3232
# TX
33-
tx_reg = Signal(BV(8))
34-
tx_bitcount = Signal(BV(4))
35-
tx_count16 = Signal(BV(4))
33+
tx_reg = Signal(8)
34+
tx_bitcount = Signal(4)
35+
tx_count16 = Signal(4)
3636
tx_busy = self._tx_event.trigger
3737
sync += [
3838
If(self._rxtx.re,
@@ -66,9 +66,9 @@ def get_fragment(self):
6666
rx.eq(rx0)
6767
]
6868
rx_r = Signal()
69-
rx_reg = Signal(BV(8))
70-
rx_bitcount = Signal(BV(4))
71-
rx_count16 = Signal(BV(4))
69+
rx_reg = Signal(8)
70+
rx_bitcount = Signal(4)
71+
rx_count16 = Signal(4)
7272
rx_busy = Signal()
7373
rx_done = self._rx_event.trigger
7474
rx_data = self._rxtx.w

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