m-labs · Jul 15, 2013 · Jul 15, 2013
diff --git a/milkymist/lasmicon/bankmachine.py b/milkymist/lasmicon/bankmachine.py
@@ -1,5 +1,4 @@
 from migen.fhdl.std import *
-from migen.bus.asmibus import *
 from migen.genlib.roundrobin import *
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import optree

diff --git a/tb/asmicon/asmicon.py b/tb/asmicon/asmicon.py
diff --git a/tb/asmicon/asmicon_wb.py b/tb/asmicon/asmicon_wb.py
diff --git a/tb/asmicon/bankmachine.py b/tb/asmicon/bankmachine.py
diff --git a/tb/asmicon/selector.py b/tb/asmicon/selector.py
diff --git a/tb/lasmicon/bankmachine.py b/tb/lasmicon/bankmachine.py
@@ -0,0 +1,44 @@
+from migen.fhdl.std import *
+from migen.bus.lasmibus import *
+from migen.sim.generic import Simulator, TopLevel
+
+from milkymist.lasmicon.bankmachine import *
+
+from common import sdram_geom, sdram_timing, CommandLogger
+
+def my_generator():
+	for x in range(10):
+		yield True, x
+	for x in range(10):
+		yield False, 128*x
+
+class TB(Module):
+	def __init__(self):
+		self.req = Interface(32, 32, 1,
+			sdram_timing.req_queue_size, sdram_timing.read_latency, sdram_timing.write_latency)
+		self.submodules.dut = BankMachine(sdram_geom, sdram_timing, 2, 0, self.req)
+		self.submodules.logger = CommandLogger(self.dut.cmd, True)
+		self.generator = my_generator()
+		self.dat_ack_cnt = 0
+
+	def do_simulation(self, s):
+		if s.rd(self.req.dat_ack):
+			self.dat_ack_cnt += 1
+		if s.rd(self.req.req_ack):
+			try:
+				we, adr = next(self.generator)
+			except StopIteration:
+				s.wr(self.req.stb, 0)
+				if not s.rd(self.req.lock):
+					s.interrupt = True
+					print("data ack count: {0}".format(self.dat_ack_cnt))
+				return
+			s.wr(self.req.adr, adr)
+			s.wr(self.req.we, we)
+			s.wr(self.req.stb, 1)
+
+def main():	
+	sim = Simulator(TB(), TopLevel("my.vcd"))
+	sim.run()
+
+main()
diff --git a/tb/asmicon/common.py → tb/lasmicon/common.py b/tb/asmicon/common.py → tb/lasmicon/common.py
@@ -4,7 +4,7 @@
 from migen.fhdl.std import *
 from migen.sim.generic import Proxy
 
-from milkymist import asmicon
+from milkymist import lasmicon
 
 MHz = 1000000
 clk_freq = (83 + Fraction(1, 3))*MHz
@@ -15,28 +15,31 @@ def ns(t, margin=True):
 		t += clk_period_ns/2
 	return ceil(t/clk_period_ns)
 
-sdram_phy = asmicon.PhySettings(
+sdram_phy = lasmicon.PhySettings(
+	type="DDR",
 	dfi_d=64, 
 	nphases=2,
 	rdphase=0,
-	wrphase=1
+	wrphase=1,
+	cl=3
 )
-sdram_geom = asmicon.GeomSettings(
+sdram_geom = lasmicon.GeomSettings(
 	bank_a=2,
 	row_a=13,
 	col_a=10
 )
-sdram_timing = asmicon.TimingSettings(
+sdram_timing = lasmicon.TimingSettings(
 	tRP=ns(15),
 	tRCD=ns(15),
 	tWR=ns(15),
+	tWTR=2,
 	tREFI=ns(7800, False),
 	tRFC=ns(70),
 
-	CL=3,
-	rd_delay=4,
+	read_latency=5,
+	write_latency=0,
 
-	slot_time=16,
+	req_queue_size=8,
 	read_time=32,
 	write_time=16
 )
@@ -69,62 +72,28 @@ def decode_sdram(ras_n, cas_n, we_n, bank, address):
 		elts.append("LMR")
 	return elts
 
-class CommandLogger:
+class CommandLogger(Module):
 	def __init__(self, cmd, rw=False):
 		self.cmd = cmd
-		self.rw = rw
+		if rw:
+			self.comb += self.cmd.ack.eq(1)
 
 	def do_simulation(self, s):
 		elts = ["@" + str(s.cycle_counter)]
 		cmdp = Proxy(s, self.cmd)
 		elts += decode_sdram(cmdp.ras_n, cmdp.cas_n, cmdp.we_n, cmdp.ba, cmdp.a)
 		if len(elts) > 1:
 			print("\t".join(elts))
-
-	def get_fragment(self):
-		if self.rw:
-			comb = [self.cmd.ack.eq(1)]
-		else:
-			comb = []
-		return Fragment(comb, sim=[self.do_simulation])
 
-class DFILogger:
+class DFILogger(Module):
 	def __init__(self, dfi):
 		self.dfi = dfi
 
 	def do_simulation(self, s):
 		dfip = Proxy(s, self.dfi)
 
 		for i, p in enumerate(dfip.phases):
-			elts = ["PH=" + str(i) + "\t @" + str(s.cycle_counter)]
+			elts = ["@" + str(s.cycle_counter) + ":" + str(i)]
 			elts += decode_sdram(p.ras_n, p.cas_n, p.we_n, p.bank, p.address)
 			if len(elts) > 1:
 				print("\t".join(elts))
-
-	def get_fragment(self):
-		return Fragment(sim=[self.do_simulation])
-
-class SlotsLogger:
-	def __init__(self, slicer, slots):
-		self.slicer = slicer
-		self.slots = slots
-
-	def do_simulation(self, sim):
-		state_strs = ["EMPTY", "PEND", "PRCESS"]
-		rw_strs = ["RD", "WR"]
-		print("\t" + "\t".join([str(x) for x in range(len(self.slots))]))
-		print("State:\t" + "\t".join([state_strs[sim.rd(s.state)] for s in self.slots]))
-		print("RW:\t" + "\t".join([rw_strs[sim.rd(s.we)] for s in self.slots]))
-		print("Row:\t" + "\t".join([str(self.slicer.row(sim.rd(s.adr))) for s in self.slots]))
-		print("Bank:\t" + "\t".join([str(self.slicer.bank(sim.rd(s.adr))) for s in self.slots]))
-		print("Col:\t" + "\t".join([str(self.slicer.col(sim.rd(s.adr))) for s in self.slots]))
-		times = []
-		for s in self.slots:
-			if s.time:
-				times.append(str(sim.rd(s._counter)) + "/" + str(s.time))
-			else:
-				times.append("N/A")
-		print("Time:\t" + "\t".join(times))
-
-	def get_fragment(self):
-		return Fragment(sim=[self.do_simulation])