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base repository: m-labs/misoc
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compare: 60124be293f5
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  • 4 commits
  • 6 files changed
  • 1 contributor

Commits on Apr 1, 2015

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4 changes: 3 additions & 1 deletion misoclib/com/liteeth/example_designs/make.py
Original file line number Diff line number Diff line change
@@ -72,6 +72,8 @@ def _get_args():
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs)
soc.finalize()
memory_regions = soc.get_memory_regions()
csr_regions = soc.get_csr_regions()

# decode actions
action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
@@ -121,7 +123,7 @@ def _get_args():
subprocess.call(["rm", "-rf", "build/*"])

if actions["build-csr-csv"]:
csr_csv = cpuif.get_csr_csv(soc.csr_regions)
csr_csv = cpuif.get_csr_csv(csr_regions)
write_to_file(args.csr_csv, csr_csv)

if actions["build-bitstream"]:
7 changes: 4 additions & 3 deletions misoclib/com/liteeth/example_designs/targets/base.py
Original file line number Diff line number Diff line change
@@ -23,14 +23,15 @@ def __init__(self, platform, clk_freq=166*1000000,
mac_address=0x10e2d5000000,
ip_address="192.168.0.42"):
clk_freq = int((1/(platform.default_clk_period))*1000000000)
self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
SoC.__init__(self, platform, clk_freq, self.uart2wb,
with_cpu=False,
SoC.__init__(self, platform, clk_freq,
cpu_type="none",
with_csr=True, csr_data_width=32,
with_uart=False,
with_identifier=True,
with_timer=False
)
self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))

# wishbone SRAM (to test Wishbone over UART and Etherbone)
4 changes: 3 additions & 1 deletion misoclib/mem/litesata/example_designs/make.py
Original file line number Diff line number Diff line change
@@ -69,6 +69,8 @@ def _get_args():
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs)
soc.finalize()
memory_regions = soc.get_memory_regions()
csr_regions = soc.get_csr_regions()

# decode actions
action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
@@ -124,7 +126,7 @@ def _get_args():
subprocess.call(["rm", "-rf", "build/*"])

if actions["build-csr-csv"]:
csr_csv = cpuif.get_csr_csv(soc.get_csr_regions())
csr_csv = cpuif.get_csr_csv(csr_regions)
write_to_file(args.csr_csv, csr_csv)

if actions["build-core"]:
2 changes: 1 addition & 1 deletion misoclib/soc/sdram.py
Original file line number Diff line number Diff line change
@@ -78,7 +78,7 @@ def register_sdram_phy(self, phy):
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))

def do_finalize(self):
if not self.integrated_ram_size:
if not self.integrated_main_ram_size:
if not self._sdram_phy_registered:
raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
SoC.do_finalize(self)
4 changes: 3 additions & 1 deletion misoclib/tools/litescope/example_designs/make.py
Original file line number Diff line number Diff line change
@@ -72,6 +72,8 @@ def _get_args():
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs)
soc.finalize()
memory_regions = soc.get_memory_regions()
csr_regions = soc.get_csr_regions()

# decode actions
action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
@@ -130,7 +132,7 @@ def _get_args():
subprocess.call(["rm", "-rf", "build/*"])

if actions["build-csr-csv"]:
csr_csv = cpuif.get_csr_csv(soc.csr_regions)
csr_csv = cpuif.get_csr_csv(csr_regions)
write_to_file(args.csr_csv, csr_csv)

if actions["build-bitstream"]:
7 changes: 4 additions & 3 deletions misoclib/tools/litescope/example_designs/targets/simple.py
Original file line number Diff line number Diff line change
@@ -16,14 +16,15 @@ class LiteScopeSoC(SoC, AutoCSR):
csr_map.update(SoC.csr_map)
def __init__(self, platform):
clk_freq = int((1/(platform.default_clk_period))*1000000000)
self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
SoC.__init__(self, platform, clk_freq, self.uart2wb,
with_cpu=False,
SoC.__init__(self, platform, clk_freq,
cpu_type="none",
with_csr=True, csr_data_width=32,
with_uart=False,
with_identifier=True,
with_timer=False
)
self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))

self.submodules.io = LiteScopeIO(8)