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minor cleanups
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sbourdeauducq committed Apr 2, 2015
1 parent bbdbf87 commit 382ed01
Showing 2 changed files with 4 additions and 4 deletions.
2 changes: 1 addition & 1 deletion misoclib/mem/sdram/core/__init__.py
Original file line number Diff line number Diff line change
@@ -19,7 +19,7 @@ def __init__(self, phy, geom_settings, timing_settings, controller_settings, **k
controller_settings, **kwargs)
self.comb += Record.connect(controller.dfi, self.dfii.slave)

self.submodules.crossbar = crossbar = lasmixbar.LASMIxbar([controller.lasmic], controller.nrowbits)
self.submodules.crossbar = lasmixbar.LASMIxbar([controller.lasmic], controller.nrowbits)

# MINICON
elif isinstance(controller_settings, minicon.MiniconSettings):
6 changes: 3 additions & 3 deletions misoclib/soc/sdram.py
Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
from migen.fhdl.std import *
from migen.bus import wishbone, csr
from migen.bus import wishbone
from migen.genlib.record import *

from misoclib.mem.sdram.core import SDRAMCore
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
from misoclib.mem.sdram.core.minicon import MiniconSettings
from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
from misoclib.soc import SoC, mem_decoder
from misoclib.soc import SoC

class SDRAMSoC(SoC):
csr_map = {
@@ -54,7 +54,7 @@ def register_sdram_phy(self, phy):
self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())

l2_size = self.sdram_controller_settings.l2_size
if l2_size != 0:
if l2_size:
# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
# Remove this workaround when fixed by Xilinx.

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