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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 4b66e3108a3f
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  • 3 commits
  • 5 files changed
  • 1 contributor

Commits on Apr 2, 2015

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Showing with 142 additions and 10 deletions.
  1. +2 −0 artiq/gateware/amp/__init__.py
  2. +53 −0 artiq/gateware/amp/kernel_cpu.py
  3. +23 −0 artiq/gateware/amp/mailbox.py
  4. +24 −0 soc/runtime/test_mode.c
  5. +40 −10 soc/targets/artiq_kc705.py
2 changes: 2 additions & 0 deletions artiq/gateware/amp/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
from artiq.gateware.amp.kernel_cpu import KernelCPU
from artiq.gateware.amp.mailbox import Mailbox
53 changes: 53 additions & 0 deletions artiq/gateware/amp/kernel_cpu.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,53 @@
from migen.fhdl.std import *
from migen.bank.description import *
from migen.bus import wishbone

from misoclib.cpu import mor1kx
from misoclib.mem.sdram.frontend.wishbone2lasmi import WB2LASMI
from misoclib.soc import mem_decoder


class KernelCPU(Module):
def __init__(self, platform, lasmim,
exec_address=0x41000000,
main_mem_origin=0x40000000,
l2_size=8192):
self._reset = CSRStorage(reset=1)

# # #

self._wb_slaves = []

# CPU core
self.clock_domains.cd_sys_kernel = ClockDomain()
self.comb += [
self.cd_sys_kernel.clk.eq(ClockSignal()),
self.cd_sys_kernel.rst.eq(self._reset.storage)
]
self.submodules.cpu = RenameClockDomains(
mor1kx.MOR1KX(platform, exec_address),
"sys_kernel")

# DRAM access
# XXX Vivado 2014.X workaround
from mibuild.xilinx.vivado import XilinxVivadoToolchain
if isinstance(platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.wishbone2lasmi = FullMemoryWE(
WB2LASMI(l2_size//4, lasmim))
else:
self.submodules.wishbone2lasmi = WB2LASMI(l2_size//4, lasmim)
self.add_wb_slave(mem_decoder(main_mem_origin),
self.wishbone2lasmi.wishbone)

def get_csrs(self):
return [self._reset]

def do_finalize(self):
self.submodules.wishbonecon = wishbone.InterconnectShared(
[self.cpu.ibus, self.cpu.dbus], self._wb_slaves, register=True)

def add_wb_slave(self, address_decoder, interface):
if self.finalized:
raise FinalizeError
self._wb_slaves.append((address_decoder, interface))
23 changes: 23 additions & 0 deletions artiq/gateware/amp/mailbox.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
from migen.fhdl.std import *
from migen.bus import wishbone


class Mailbox(Module):
def __init__(self):
self.i1 = wishbone.Interface()
self.i2 = wishbone.Interface()

# # #

value = Signal(32)
for i in self.i1, self.i2:
self.sync += [
i.ack.eq(0),
If(i.cyc & i.stb & ~i.ack, i.ack.eq(1)),

i.dat_r.eq(value),
If(i.cyc & i.stb & i.we,
[If(i.sel[j], value[j*8:j*8+8].eq(i.dat_w[j*8:j*8+8]))
for j in range(4)]
)
]
24 changes: 24 additions & 0 deletions soc/runtime/test_mode.c
Original file line number Diff line number Diff line change
@@ -305,6 +305,28 @@ static char *get_token(char **str)
return d;
}

static const unsigned int test_program[] = {
0x1860dead, // l.movhi r3,0xdead
0x1880d000, // l.movhi r4,0xd000
0xa863beef, // l.ori r3,r3,0xbeef
0xd4041800, // l.sw 0(r4),r3
0x00000000, // l.j +0
0x15000000, // l.nop
};

static void cputest(void)
{
int i;

kernel_cpu_reset_write(1);
MMPTR(0xd0000000) = 0;
memcpy((void *)0x41000000, test_program, sizeof(test_program));
flush_l2_cache();
kernel_cpu_reset_write(0);
for(i=0;i<10;i++)
printf("%08x\n", MMPTR(0xd0000000));
}

static void do_command(char *c)
{
char *token;
@@ -327,6 +349,8 @@ static void do_command(char *c)
else if(strcmp(token, "ddsftw") == 0) ddsftw(get_token(&c), get_token(&c));
else if(strcmp(token, "ddstest") == 0) ddstest(get_token(&c));

else if(strcmp(token, "cputest") == 0) cputest();

else if(strcmp(token, "") != 0)
printf("Command not found\n");
}
50 changes: 40 additions & 10 deletions soc/targets/artiq_kc705.py
Original file line number Diff line number Diff line change
@@ -4,9 +4,10 @@
from mibuild.generic_platform import *

from misoclib.cpu.peripherals import gpio
from misoclib.soc import mem_decoder
from targets.kc705 import BaseSoC

from artiq.gateware import rtio, ad9858
from artiq.gateware import amp, rtio, ad9858


_tester_io = [
@@ -67,15 +68,14 @@ def __init__(self, platform, rtio_internal_clk):
o_O=self.cd_rtio.clk)


class ARTIQSoC(BaseSoC):
class _ARTIQSoCPeripherals(BaseSoC):
csr_map = {
"rtio": None, # mapped on Wishbone instead
"rtiocrg": 13
}
csr_map.update(BaseSoC.csr_map)

def __init__(self, platform, cpu_type="or1k", with_test_gen=False,
**kwargs):
def __init__(self, platform, cpu_type="or1k", **kwargs):
BaseSoC.__init__(self, platform,
cpu_type=cpu_type, **kwargs)
platform.add_extension(_tester_io)
@@ -100,14 +100,44 @@ def __init__(self, platform, cpu_type="or1k", with_test_gen=False,
clk_freq=125000000,
ififo_depth=512)

dds_pads = platform.request("dds")
self.submodules.dds = ad9858.AD9858(dds_pads)
self.comb += dds_pads.fud_n.eq(~fud)


class ARTIQSoCBasic(_ARTIQSoCPeripherals):
def __init__(self, *args, **kwargs):
_ARTIQSoCPeripherals.__init__(self, *args, **kwargs)

rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
self.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)

dds_pads = platform.request("dds")
self.submodules.dds = ad9858.AD9858(dds_pads)
self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
self.comb += dds_pads.fud_n.eq(~fud)
self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)


class ARTIQSoC(_ARTIQSoCPeripherals):
csr_map = {
"kernel_cpu": 14
}
csr_map.update(_ARTIQSoCPeripherals.csr_map)

def __init__(self, platform, *args, **kwargs):
_ARTIQSoCPeripherals.__init__(self, platform, *args, **kwargs)

self.submodules.kernel_cpu = amp.KernelCPU(
platform, self.sdram.crossbar.get_master())
self.submodules.mailbox = amp.Mailbox()
self.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i1)
self.kernel_cpu.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i2)

rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)

self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)


default_subtarget = ARTIQSoC
default_subtarget = ARTIQSoCBasic