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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: be20fbabe451
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Mar 28, 2015

  1. Copy the full SHA
    0649ded View commit details
  2. soc: limit main_ram_size to 256MB (we should modify mem_map to allow …

    …larger memories, this was the probably ARTIQ runtime issue....!!)
    enjoy-digital committed Mar 28, 2015
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    be20fba View commit details
Showing with 8 additions and 6 deletions.
  1. +8 −6 misoclib/soc/sdram.py
14 changes: 8 additions & 6 deletions misoclib/soc/sdram.py
Original file line number Diff line number Diff line change
@@ -36,6 +36,14 @@ def register_sdram_phy(self, phy):
# Core
self.submodules.sdram = SDRAMCore(phy, phy.module.geom_settings, phy.module.timing_settings, self.sdram_controller_settings)

dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2
sdram_width = phy.settings.dfi_databits//dfi_databits_divisor
main_ram_size = 2**(phy.module.geom_settings.bankbits+
phy.module.geom_settings.rowbits+
phy.module.geom_settings.colbits)*sdram_width//8
# XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories.
main_ram_size = min(main_ram_size, 256*1024*1024)

# LASMICON frontend
if isinstance(self.sdram_controller_settings, LASMIconSettings):
if self.sdram_controller_settings.with_bandwidth:
@@ -57,16 +65,10 @@ def register_sdram_phy(self, phy):
else:
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master())
lasmic = self.sdram.controller.lasmic
main_ram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size)

# MINICON frontend
elif isinstance(self.sdram_controller_settings, MiniconSettings):
sdram_width = flen(self.sdram.controller.bus.dat_r)
main_ram_size = 2**(phy.module.geom_settings.bankbits+
phy.module.geom_settings.rowbits+
phy.module.geom_settings.colbits)*sdram_width//8

if sdram_width == 32:
self.register_mem("main_ram", self.mem_map["main_ram"], self.sdram.controller.bus, main_ram_size)
elif sdram_width < 32: