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litesata: adapt to new SoC API
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sbourdeauducq committed Apr 1, 2015
1 parent 9599eb6 commit 6e2a662
Showing 2 changed files with 5 additions and 4 deletions.
2 changes: 1 addition & 1 deletion misoclib/mem/litesata/example_designs/make.py
Original file line number Diff line number Diff line change
@@ -124,7 +124,7 @@ def _get_args():
subprocess.call(["rm", "-rf", "build/*"])

if actions["build-csr-csv"]:
csr_csv = cpuif.get_csr_csv(soc.csr_regions)
csr_csv = cpuif.get_csr_csv(soc.get_csr_regions())
write_to_file(args.csr_csv, csr_csv)

if actions["build-core"]:
7 changes: 4 additions & 3 deletions misoclib/mem/litesata/example_designs/targets/bist.py
Original file line number Diff line number Diff line change
@@ -89,14 +89,15 @@ class BISTSoC(SoC, AutoCSR):
csr_map.update(SoC.csr_map)
def __init__(self, platform):
clk_freq = 166*1000000
self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
SoC.__init__(self, platform, clk_freq, self.uart2wb,
with_cpu=False,
SoC.__init__(self, platform, clk_freq,
cpu_type="none",
with_csr=True, csr_data_width=32,
with_uart=False,
with_identifier=True,
with_timer=False
)
self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = _CRG(platform)

# SATA PHY/Core/Frontend

1 comment on commit 6e2a662

@enjoy-digital
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Thanks for the SoC cleanup! I'll adapt the others core.

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